diff options
| author | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
|---|---|---|
| committer | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
| commit | 96d6da4e252b06dcfdc041e7df23e86161c33007 (patch) | |
| tree | a262f59bb1db7ec7819acae435f5049cbe5e2354 /DSP/DSP_Lib_TestSuite/DspLibTest_FVP | |
| parent | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (diff) | |
| download | st-cmsis-core-lowfat-master.tar.gz st-cmsis-core-lowfat-master.tar.bz2 st-cmsis-core-lowfat-master.zip | |
Diffstat (limited to 'DSP/DSP_Lib_TestSuite/DspLibTest_FVP')
25 files changed, 13796 insertions, 4807 deletions
diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx index 5145d60..fbd1ae9 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx @@ -101,7 +101,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -138,7 +140,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"../cortexM0l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -185,6 +187,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -268,7 +274,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -285,7 +293,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"../cortexM3l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -332,6 +340,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -415,7 +427,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -432,7 +446,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"../cortexM4l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -479,6 +493,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -562,7 +580,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -599,7 +619,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -646,6 +666,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -729,7 +753,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -766,7 +792,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -813,6 +839,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -896,7 +926,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -933,7 +965,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfsp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -980,6 +1012,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1063,7 +1099,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -1080,7 +1118,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfdp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1127,6 +1165,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1210,6 +1252,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1242,7 +1286,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1289,6 +1333,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1372,6 +1420,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1389,7 +1439,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1436,6 +1486,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1519,6 +1573,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1551,7 +1607,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_FP_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1598,141 +1654,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> - </TargetOption> - </Target> - - <Target> - <TargetName>ARMv8MMLlfdp.DoNotUse</TargetName> - <ToolsetNumber>0x4</ToolsetNumber> - <ToolsetName>ARM-ADS</ToolsetName> - <TargetOption> - <CLKADS>12000000</CLKADS> - <OPTTT> - <gFlags>0</gFlags> - <BeepAtEnd>1</BeepAtEnd> - <RunSim>1</RunSim> - <RunTarget>0</RunTarget> - <RunAbUc>0</RunAbUc> - </OPTTT> - <OPTHX> - <HexSelection>1</HexSelection> - <FlashByte>65535</FlashByte> - <HexRangeLowAddress>0</HexRangeLowAddress> - <HexRangeHighAddress>0</HexRangeHighAddress> - <HexOffset>0</HexOffset> - </OPTHX> - <OPTLEX> - <PageWidth>79</PageWidth> - <PageLength>66</PageLength> - <TabStop>8</TabStop> - <ListingPath>.\IntermediateFiles\ARMv8MMLlfdp\</ListingPath> - </OPTLEX> - <ListingPage> - <CreateCListing>1</CreateCListing> - <CreateAListing>1</CreateAListing> - <CreateLListing>1</CreateLListing> - <CreateIListing>0</CreateIListing> - <AsmCond>1</AsmCond> - <AsmSymb>1</AsmSymb> - <AsmXref>0</AsmXref> - <CCond>1</CCond> - <CCode>0</CCode> - <CListInc>0</CListInc> - <CSymb>0</CSymb> - <LinkerCodeListing>0</LinkerCodeListing> - </ListingPage> - <OPTXL> - <LMap>1</LMap> - <LComments>1</LComments> - <LGenerateSymbols>1</LGenerateSymbols> - <LLibSym>1</LLibSym> - <LLines>1</LLines> - <LLocSym>1</LLocSym> - <LPubSym>1</LPubSym> - <LXref>0</LXref> - <LExpSel>0</LExpSel> - </OPTXL> - <OPTFL> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <IsCurrentTarget>0</IsCurrentTarget> - </OPTFL> - <CpuCode>7</CpuCode> - <DebugOpt> - <uSim>1</uSim> - <uTrg>0</uTrg> - <sLdApp>1</sLdApp> - <sGomain>1</sGomain> - <sRbreak>1</sRbreak> - <sRwatch>1</sRwatch> - <sRmem>1</sRmem> - <sRfunc>1</sRfunc> - <sRbox>1</sRbox> - <tLdApp>1</tLdApp> - <tGomain>0</tGomain> - <tRbreak>1</tRbreak> - <tRwatch>1</tRwatch> - <tRmem>1</tRmem> - <tRfunc>0</tRfunc> - <tRbox>1</tRbox> - <tRtrace>1</tRtrace> - <sRSysVw>1</sRSysVw> - <tRSysVw>1</tRSysVw> - <sRunDeb>0</sRunDeb> - <sLrtime>0</sLrtime> - <bEvRecOn>1</bEvRecOn> - <nTsel>-1</nTsel> - <sDll></sDll> - <sDllPa></sDllPa> - <sDlgDll></sDlgDll> - <sDlgPa></sDlgPa> - <sIfile></sIfile> - <tDll></tDll> - <tDllPa></tDllPa> - <tDlgDll></tDlgDll> - <tDlgPa></tDlgPa> - <tIfile></tIfile> - <pMon></pMon> - </DebugOpt> - <Breakpoint/> - <Tracepoint> - <THDelay>0</THDelay> - </Tracepoint> - <DebugFlag> - <trace>0</trace> - <periodic>0</periodic> - <aLwin>0</aLwin> - <aCover>0</aCover> - <aSer1>0</aSer1> - <aSer2>0</aSer2> - <aPa>0</aPa> - <viewmode>0</viewmode> - <vrSel>0</vrSel> - <aSym>0</aSym> - <aTbox>0</aTbox> - <AscS1>0</AscS1> - <AscS2>0</AscS2> - <AscS3>0</AscS3> - <aSer3>0</aSer3> - <eProf>0</eProf> - <aLa>0</aLa> - <aPa1>0</aPa1> - <AscS4>0</AscS4> - <aSer4>0</aSer4> - <StkLoc>0</StkLoc> - <TrcWin>0</TrcWin> - <newCpu>0</newCpu> - <uProt>0</uProt> - </DebugFlag> - <LintExecutable></LintExecutable> - <LintConfigFile></LintConfigFile> - <bLintAuto>0</bLintAuto> - <bAutoGenD>0</bAutoGenD> - <LntExFlags>0</LntExFlags> - <pMisraName></pMisraName> - <pszMrule></pszMrule> - <pSingCmds></pSingCmds> - <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1816,6 +1741,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1848,7 +1775,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1895,6 +1822,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1978,6 +1909,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -2010,7 +1943,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -2057,141 +1990,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> - </TargetOption> - </Target> - - <Target> - <TargetName>ARMv8MMLldfdp.DoNotUse</TargetName> - <ToolsetNumber>0x4</ToolsetNumber> - <ToolsetName>ARM-ADS</ToolsetName> - <TargetOption> - <CLKADS>12000000</CLKADS> - <OPTTT> - <gFlags>0</gFlags> - <BeepAtEnd>1</BeepAtEnd> - <RunSim>1</RunSim> - <RunTarget>0</RunTarget> - <RunAbUc>0</RunAbUc> - </OPTTT> - <OPTHX> - <HexSelection>1</HexSelection> - <FlashByte>65535</FlashByte> - <HexRangeLowAddress>0</HexRangeLowAddress> - <HexRangeHighAddress>0</HexRangeHighAddress> - <HexOffset>0</HexOffset> - </OPTHX> - <OPTLEX> - <PageWidth>79</PageWidth> - <PageLength>66</PageLength> - <TabStop>8</TabStop> - <ListingPath>.\IntermediateFiles\ARMv8MMLldfdp\</ListingPath> - </OPTLEX> - <ListingPage> - <CreateCListing>1</CreateCListing> - <CreateAListing>1</CreateAListing> - <CreateLListing>1</CreateLListing> - <CreateIListing>0</CreateIListing> - <AsmCond>1</AsmCond> - <AsmSymb>1</AsmSymb> - <AsmXref>0</AsmXref> - <CCond>1</CCond> - <CCode>0</CCode> - <CListInc>0</CListInc> - <CSymb>0</CSymb> - <LinkerCodeListing>0</LinkerCodeListing> - </ListingPage> - <OPTXL> - <LMap>1</LMap> - <LComments>1</LComments> - <LGenerateSymbols>1</LGenerateSymbols> - <LLibSym>1</LLibSym> - <LLines>1</LLines> - <LLocSym>1</LLocSym> - <LPubSym>1</LPubSym> - <LXref>0</LXref> - <LExpSel>0</LExpSel> - </OPTXL> - <OPTFL> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <IsCurrentTarget>0</IsCurrentTarget> - </OPTFL> - <CpuCode>7</CpuCode> - <DebugOpt> - <uSim>1</uSim> - <uTrg>0</uTrg> - <sLdApp>1</sLdApp> - <sGomain>1</sGomain> - <sRbreak>1</sRbreak> - <sRwatch>1</sRwatch> - <sRmem>1</sRmem> - <sRfunc>1</sRfunc> - <sRbox>1</sRbox> - <tLdApp>1</tLdApp> - <tGomain>0</tGomain> - <tRbreak>1</tRbreak> - <tRwatch>1</tRwatch> - <tRmem>1</tRmem> - <tRfunc>0</tRfunc> - <tRbox>1</tRbox> - <tRtrace>1</tRtrace> - <sRSysVw>1</sRSysVw> - <tRSysVw>1</tRSysVw> - <sRunDeb>0</sRunDeb> - <sLrtime>0</sLrtime> - <bEvRecOn>1</bEvRecOn> - <nTsel>-1</nTsel> - <sDll></sDll> - <sDllPa></sDllPa> - <sDlgDll></sDlgDll> - <sDlgPa></sDlgPa> - <sIfile></sIfile> - <tDll></tDll> - <tDllPa></tDllPa> - <tDlgDll></tDlgDll> - <tDlgPa></tDlgPa> - <tIfile></tIfile> - <pMon></pMon> - </DebugOpt> - <Breakpoint/> - <Tracepoint> - <THDelay>0</THDelay> - </Tracepoint> - <DebugFlag> - <trace>0</trace> - <periodic>0</periodic> - <aLwin>0</aLwin> - <aCover>0</aCover> - <aSer1>0</aSer1> - <aSer2>0</aSer2> - <aPa>0</aPa> - <viewmode>0</viewmode> - <vrSel>0</vrSel> - <aSym>0</aSym> - <aTbox>0</aTbox> - <AscS1>0</AscS1> - <AscS2>0</AscS2> - <AscS3>0</AscS3> - <aSer3>0</aSer3> - <eProf>0</eProf> - <aLa>0</aLa> - <aPa1>0</aPa1> - <AscS4>0</AscS4> - <aSer4>0</aSer4> - <StkLoc>0</StkLoc> - <TrcWin>0</TrcWin> - <newCpu>0</newCpu> - <uProt>0</uProt> - </DebugFlag> - <LintExecutable></LintExecutable> - <LintConfigFile></LintConfigFile> - <bLintAuto>0</bLintAuto> - <bAutoGenD>0</bAutoGenD> - <LntExFlags>0</LntExFlags> - <pMisraName></pMisraName> - <pszMrule></pszMrule> - <pSingCmds></pSingCmds> - <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -2705,7 +2507,7 @@ <GroupNumber>8</GroupNumber> <FileNumber>38</FileNumber> <FileType>1</FileType> - <tvExp>0</tvExp> + <tvExp>1</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <bDave2>0</bDave2> <PathWithFileName>..\..\Common\src\controller_tests\pid_reset_tests.c</PathWithFileName> diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx index 7296f06..bc06615 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx @@ -10,11 +10,13 @@ <TargetName>cortexM0l</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM0</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -131,7 +133,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -182,6 +184,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -322,6 +325,7 @@ <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> <v6Lang>0</v6Lang> <v6LangP>0</v6LangP> @@ -332,9 +336,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM0</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -349,8 +353,8 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM0</MiscControls> - <Define>ARM_MATH_CM0</Define> + <MiscControls>--cpreproc --cpreproc_opts=-D,ARMCM0</MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -365,7 +369,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCC\armcc5_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -851,11 +855,12 @@ <TargetName>cortexM3l</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM3</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -911,8 +916,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name>python Scripts/get_ref_and_dsp_libs.py ARM M3l</UserProg1Name> - <UserProg2Name>python Scripts/get_ref_and_dsp_libs.py GCC M3l</UserProg2Name> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -972,7 +977,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -1023,6 +1028,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -1163,6 +1169,7 @@ <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> <v6Lang>0</v6Lang> <v6LangP>0</v6LangP> @@ -1173,9 +1180,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM3</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -1190,8 +1197,8 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM3</MiscControls> - <Define>ARM_MATH_CM3</Define> + <MiscControls>--cpreproc --cpreproc_opts=-D,ARMCM3</MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -1206,7 +1213,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCC\armcc5_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -1692,11 +1699,12 @@ <TargetName>cortexM4l</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM4</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -1752,8 +1760,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name>python Scripts/get_ref_and_dsp_libs.py ARM M4l</UserProg1Name> - <UserProg2Name>python Scripts/get_ref_and_dsp_libs.py GCC M4l</UserProg2Name> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -1813,7 +1821,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -1864,6 +1872,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -2004,6 +2013,7 @@ <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> <v6Lang>0</v6Lang> <v6LangP>0</v6LangP> @@ -2014,9 +2024,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM4</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -2031,8 +2041,8 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM4</MiscControls> - <Define>ARM_MATH_CM4</Define> + <MiscControls>--cpreproc --cpreproc_opts=-D,ARMCM4</MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -2047,7 +2057,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCC\armcc5_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -2533,11 +2543,12 @@ <TargetName>cortexM4lf</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM4_FP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -2593,8 +2604,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name>python Scripts/get_ref_and_dsp_libs.py ARM M4lf</UserProg1Name> - <UserProg2Name>python Scripts/get_ref_and_dsp_libs.py GCC M4lf</UserProg2Name> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -2654,7 +2665,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -2705,6 +2716,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -2845,6 +2857,7 @@ <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> <v6Lang>0</v6Lang> <v6LangP>0</v6LangP> @@ -2855,9 +2868,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM4 __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -2872,8 +2885,8 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM4</MiscControls> - <Define>ARM_MATH_CM4</Define> + <MiscControls>--cpreproc --cpreproc_opts=-D,ARMCM4</MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -2888,7 +2901,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCC\armcc5_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -3374,11 +3387,12 @@ <TargetName>cortexM7l</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM7</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -3434,8 +3448,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name>python Scripts/get_ref_and_dsp_libs.py ARM M4l</UserProg1Name> - <UserProg2Name>python Scripts/get_ref_and_dsp_libs.py GCC M4l</UserProg2Name> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -3495,7 +3509,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -3546,6 +3560,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -3686,6 +3701,7 @@ <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> <v6Lang>0</v6Lang> <v6LangP>0</v6LangP> @@ -3696,9 +3712,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM7</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -3713,8 +3729,8 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM7</MiscControls> - <Define>ARM_MATH_CM7</Define> + <MiscControls>--cpreproc --cpreproc_opts=-D,ARMCM7</MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -3729,7 +3745,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCC\armcc5_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -4215,11 +4231,12 @@ <TargetName>cortexM7lfsp</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM7_SP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -4275,8 +4292,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name>python Scripts/get_ref_and_dsp_libs.py ARM M4lf</UserProg1Name> - <UserProg2Name>python Scripts/get_ref_and_dsp_libs.py GCC M4lf</UserProg2Name> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -4336,7 +4353,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -4387,6 +4404,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -4527,6 +4545,7 @@ <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> <v6Lang>0</v6Lang> <v6LangP>0</v6LangP> @@ -4537,9 +4556,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -4554,8 +4573,8 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM7</MiscControls> - <Define>ARM_MATH_CM7</Define> + <MiscControls>--cpreproc --cpreproc_opts=-D,ARMCM7</MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -4570,7 +4589,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCC\armcc5_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -5056,11 +5075,12 @@ <TargetName>cortexM7lfdp</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM7_DP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -5177,7 +5197,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -5228,6 +5248,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>3</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -5368,6 +5389,7 @@ <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> <v6Lang>0</v6Lang> <v6LangP>0</v6LangP> @@ -5378,9 +5400,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -5395,8 +5417,8 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls>--cpreproc --cpreproc_opts=-D,ARM_MATH_CM7</MiscControls> - <Define>ARM_MATH_CM7</Define> + <MiscControls>--cpreproc --cpreproc_opts=-D,ARMCM7</MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -5411,7 +5433,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCC\armcc5_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -5897,12 +5919,13 @@ <TargetName>ARMv8MBLl</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> - <pCCUsed>6060000::V6.6::.\ARMCLANG</pCCUsed> + <pCCUsed>6110000::V6.11::.\ARMCLANG_6.11</pCCUsed> + <uAC6>1</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MBL</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -6019,7 +6042,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4097</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -6045,7 +6068,7 @@ <ldmm>1</ldmm> <ldXref>1</ldXref> <BigEnd>0</BigEnd> - <AdsALst>1</AdsALst> + <AdsALst>0</AdsALst> <AdsACrf>1</AdsACrf> <AdsANop>0</AdsANop> <AdsANot>0</AdsANot> @@ -6070,6 +6093,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -6197,32 +6221,33 @@ </ArmAdsMisc> <Cads> <interw>1</interw> - <Optim>1</Optim> + <Optim>2</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> <Ropi>0</Ropi> <Rwpi>0</Rwpi> - <wLevel>0</wLevel> + <wLevel>3</wLevel> <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> + <v6Lang>3</v6Lang> + <v6LangP>3</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> <v6Lto>0</v6Lto> <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls>-fhonor-nans</MiscControls> - <Define>ARM_MATH_ARMV8MBL</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -6235,10 +6260,10 @@ <NoWarn>0</NoWarn> <uSurpInc>0</uSurpInc> <useXO>0</useXO> - <uClangAs>0</uClangAs> + <uClangAs>1</uClangAs> <VariousControls> - <MiscControls>--cpreproc</MiscControls> - <Define>ARM_MATH_ARMV8MBL __CC_ARM</Define> + <MiscControls></MiscControls> + <Define>ARMv8MBL</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -6253,7 +6278,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCLANG\armcc6_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -6740,11 +6765,12 @@ <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <pCCUsed>6060000::V6.6::.\ARMCLANG</pCCUsed> + <uAC6>1</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -6861,7 +6887,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4097</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -6912,6 +6938,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <StupSel>8</StupSel> @@ -7039,32 +7066,33 @@ </ArmAdsMisc> <Cads> <interw>1</interw> - <Optim>1</Optim> + <Optim>2</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> <Ropi>0</Ropi> <Rwpi>0</Rwpi> - <wLevel>0</wLevel> + <wLevel>3</wLevel> <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> + <v6Lang>3</v6Lang> + <v6LangP>3</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> <v6Lto>0</v6Lto> <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> <VariousControls> - <MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls> - <Define>ARM_MATH_ARMV8MML</Define> + <MiscControls>-fhonor-nans</MiscControls> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -7077,10 +7105,10 @@ <NoWarn>0</NoWarn> <uSurpInc>0</uSurpInc> <useXO>0</useXO> - <uClangAs>0</uClangAs> + <uClangAs>1</uClangAs> <VariousControls> - <MiscControls>--cpreproc</MiscControls> - <Define>ARM_MATH_ARMV8MML __CC_ARM</Define> + <MiscControls></MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -7095,7 +7123,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCLANG\armcc6_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -7582,11 +7610,12 @@ <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <pCCUsed>6060000::V6.6::.\ARMCLANG</pCCUsed> + <uAC6>1</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML_SP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -7703,7 +7732,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> 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- <TargetStatus> - <Error>0</Error> - <ExitCodeStop>0</ExitCodeStop> - <ButtonStop>0</ButtonStop> - <NotGenerated>0</NotGenerated> - <InvalidFlash>1</InvalidFlash> - </TargetStatus> - <OutputDirectory>.\IntermediateFiles\ARMv8MMLlfdp\</OutputDirectory> - <OutputName>DspLibTest_FVP</OutputName> - <CreateExecutable>1</CreateExecutable> - <CreateLib>0</CreateLib> - <CreateHexFile>0</CreateHexFile> - <DebugInformation>1</DebugInformation> - <BrowseInformation>1</BrowseInformation> - <ListingPath>.\IntermediateFiles\ARMv8MMLlfdp\</ListingPath> - <HexFormatSelection>1</HexFormatSelection> - <Merge32K>0</Merge32K> - <CreateBatchFile>0</CreateBatchFile> - <BeforeCompile> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopU1X>0</nStopU1X> - <nStopU2X>0</nStopU2X> - </BeforeCompile> - <BeforeMake> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopB1X>0</nStopB1X> - <nStopB2X>0</nStopB2X> - </BeforeMake> - <AfterMake> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopA1X>0</nStopA1X> - <nStopA2X>0</nStopA2X> - </AfterMake> - <SelectedForBatchBuild>0</SelectedForBatchBuild> - <SVCSIdString></SVCSIdString> - </TargetCommonOption> - <CommonProperty> - <UseCPPCompiler>0</UseCPPCompiler> - <RVCTCodeConst>0</RVCTCodeConst> - <RVCTZI>0</RVCTZI> - <RVCTOtherData>0</RVCTOtherData> - <ModuleSelection>0</ModuleSelection> - <IncludeInBuild>1</IncludeInBuild> - <AlwaysBuild>0</AlwaysBuild> - <GenerateAssemblyFile>0</GenerateAssemblyFile> - <AssembleAssemblyFile>0</AssembleAssemblyFile> - <PublicsOnly>0</PublicsOnly> - <StopOnExitCode>3</StopOnExitCode> - <CustomArgument></CustomArgument> - <IncludeLibraryModules></IncludeLibraryModules> - <ComprImg>1</ComprImg> - </CommonProperty> - <DllOption> - <SimDllName></SimDllName> - <SimDllArguments></SimDllArguments> - <SimDlgDll></SimDlgDll> - <SimDlgDllArguments></SimDlgDllArguments> - <TargetDllName>SARMV8M.DLL</TargetDllName> - <TargetDllArguments> -MPU</TargetDllArguments> - <TargetDlgDll>TCM.DLL</TargetDlgDll> - <TargetDlgDllArguments>-pV8MML</TargetDlgDllArguments> - </DllOption> - <DebugOption> - <OPTHX> - <HexSelection>1</HexSelection> - <HexRangeLowAddress>0</HexRangeLowAddress> - <HexRangeHighAddress>0</HexRangeHighAddress> - <HexOffset>0</HexOffset> - <Oh166RecLen>16</Oh166RecLen> - </OPTHX> - </DebugOption> - <Utilities> - <Flash1> - <UseTargetDll>1</UseTargetDll> - <UseExternalTool>0</UseExternalTool> - <RunIndependent>0</RunIndependent> - <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging> - <Capability>1</Capability> - <DriverSelection>4097</DriverSelection> - </Flash1> - <bUseTDR>1</bUseTDR> - <Flash2>BIN\UL2V8M.DLL</Flash2> - <Flash3></Flash3> - <Flash4></Flash4> - <pFcarmOut></pFcarmOut> - <pFcarmGrp></pFcarmGrp> - <pFcArmRoot></pFcArmRoot> - <FcArmLst>0</FcArmLst> - </Utilities> - <TargetArmAds> - <ArmAdsMisc> - <GenerateListings>0</GenerateListings> - <asHll>1</asHll> - <asAsm>1</asAsm> - <asMacX>1</asMacX> - <asSyms>1</asSyms> - <asFals>1</asFals> - <asDbgD>1</asDbgD> - <asForm>1</asForm> - <ldLst>0</ldLst> - <ldmm>1</ldmm> - <ldXref>1</ldXref> - <BigEnd>0</BigEnd> - <AdsALst>0</AdsALst> - <AdsACrf>1</AdsACrf> - <AdsANop>0</AdsANop> - <AdsANot>0</AdsANot> - <AdsLLst>1</AdsLLst> - <AdsLmap>1</AdsLmap> - <AdsLcgr>1</AdsLcgr> - <AdsLsym>1</AdsLsym> - <AdsLszi>1</AdsLszi> - <AdsLtoi>1</AdsLtoi> - <AdsLsun>1</AdsLsun> - <AdsLven>1</AdsLven> - <AdsLsxf>1</AdsLsxf> - <RvctClst>0</RvctClst> - <GenPPlst>0</GenPPlst> - <AdsCpuType>"ARMV8MML"</AdsCpuType> - <RvctDeviceName></RvctDeviceName> - <mOS>0</mOS> - <uocRom>0</uocRom> - <uocRam>0</uocRam> - <hadIROM>1</hadIROM> - <hadIRAM>1</hadIRAM> - <hadXRAM>0</hadXRAM> - <uocXRam>0</uocXRam> - <RvdsVP>3</RvdsVP> - <hadIRAM2>1</hadIRAM2> - <hadIROM2>1</hadIROM2> - <StupSel>8</StupSel> - <useUlib>0</useUlib> - <EndSel>1</EndSel> - <uLtcg>0</uLtcg> - <nSecure>0</nSecure> - <RoSelD>3</RoSelD> - <RwSelD>3</RwSelD> - <CodeSel>0</CodeSel> - <OptFeed>0</OptFeed> - <NoZi1>0</NoZi1> - <NoZi2>0</NoZi2> - <NoZi3>0</NoZi3> - <NoZi4>0</NoZi4> - <NoZi5>0</NoZi5> - <Ro1Chk>0</Ro1Chk> - <Ro2Chk>0</Ro2Chk> - <Ro3Chk>0</Ro3Chk> - <Ir1Chk>1</Ir1Chk> - <Ir2Chk>0</Ir2Chk> - <Ra1Chk>0</Ra1Chk> - <Ra2Chk>0</Ra2Chk> - <Ra3Chk>0</Ra3Chk> - <Im1Chk>1</Im1Chk> - <Im2Chk>0</Im2Chk> - <OnChipMemories> - <Ocm1> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm1> - <Ocm2> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm2> - <Ocm3> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm3> - <Ocm4> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm4> - <Ocm5> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm5> - <Ocm6> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm6> - <IRAM> - <Type>0</Type> - <StartAddress>0x20000000</StartAddress> - <Size>0x20000</Size> - </IRAM> - <IROM> - <Type>1</Type> - <StartAddress>0x0</StartAddress> - <Size>0x200000</Size> - </IROM> - <XRAM> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </XRAM> - <OCR_RVCT1> - <Type>1</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT1> - <OCR_RVCT2> - <Type>1</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT2> - <OCR_RVCT3> - <Type>1</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT3> - <OCR_RVCT4> - <Type>1</Type> - <StartAddress>0x0</StartAddress> - <Size>0x200000</Size> - </OCR_RVCT4> - <OCR_RVCT5> - <Type>1</Type> - <StartAddress>0x200000</StartAddress> - <Size>0x200000</Size> - </OCR_RVCT5> - <OCR_RVCT6> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT6> - <OCR_RVCT7> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT7> - <OCR_RVCT8> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT8> - <OCR_RVCT9> - <Type>0</Type> - <StartAddress>0x20000000</StartAddress> - <Size>0x20000</Size> - </OCR_RVCT9> - <OCR_RVCT10> - <Type>0</Type> - <StartAddress>0x20200000</StartAddress> - <Size>0x20000</Size> - </OCR_RVCT10> - </OnChipMemories> - <RvctStartVector></RvctStartVector> - </ArmAdsMisc> - <Cads> - <interw>1</interw> - <Optim>1</Optim> - <oTime>0</oTime> - <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> - <Strict>0</Strict> - <EnumInt>0</EnumInt> - <PlainCh>0</PlainCh> - <Ropi>0</Ropi> - <Rwpi>0</Rwpi> - <wLevel>0</wLevel> - <uThumb>0</uThumb> - <uSurpInc>0</uSurpInc> - <uC99>0</uC99> - <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> - <v6Lto>0</v6Lto> - <v6WtE>0</v6WtE> - <v6Rtti>0</v6Rtti> - <VariousControls> - <MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls> - <Define>ARM_MATH_ARMV8MML __FPU_PRESENT=1U</Define> + <MiscControls>-fhonor-nans</MiscControls> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -8761,10 +7950,10 @@ <NoWarn>0</NoWarn> <uSurpInc>0</uSurpInc> <useXO>0</useXO> - <uClangAs>0</uClangAs> + <uClangAs>1</uClangAs> <VariousControls> - <MiscControls>--cpreproc</MiscControls> - <Define>ARM_MATH_ARMV8MML __CC_ARM</Define> + <MiscControls></MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -8779,7 +7968,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCLANG\armcc6_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -9266,11 +8455,12 @@ <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <pCCUsed>6060000::V6.6::.\ARMCLANG</pCCUsed> + <uAC6>1</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML_DSP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -9387,7 +8577,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4097</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -9438,6 +8628,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <StupSel>8</StupSel> @@ -9565,32 +8756,33 @@ </ArmAdsMisc> <Cads> <interw>1</interw> - <Optim>1</Optim> + <Optim>2</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> <Ropi>0</Ropi> <Rwpi>0</Rwpi> - <wLevel>0</wLevel> + <wLevel>3</wLevel> <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> + <v6Lang>3</v6Lang> + <v6LangP>3</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> <v6Lto>0</v6Lto> <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> <VariousControls> - <MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls> - <Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U</Define> + <MiscControls>-fhonor-nans</MiscControls> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -9603,10 +8795,10 @@ <NoWarn>0</NoWarn> <uSurpInc>0</uSurpInc> <useXO>0</useXO> - <uClangAs>0</uClangAs> + <uClangAs>1</uClangAs> <VariousControls> - <MiscControls>--cpreproc</MiscControls> - <Define>ARM_MATH_ARMV8MML __CC_ARM</Define> + <MiscControls></MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -9621,7 +8813,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCLANG\armcc6_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> @@ -10107,12 +9299,13 @@ <TargetName>ARMv8MMLldfsp</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> - <pCCUsed>6060000::V6.6::.\ARMCLANG</pCCUsed> + <pCCUsed>6110000::V6.11::.\ARMCLANG 6.11</pCCUsed> + <uAC6>1</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML_DSP_SP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -10229,7 +9422,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4097</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -10280,6 +9473,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <StupSel>8</StupSel> @@ -10407,874 +9601,33 @@ </ArmAdsMisc> <Cads> <interw>1</interw> - <Optim>1</Optim> - <oTime>0</oTime> - <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> - <Strict>0</Strict> - <EnumInt>0</EnumInt> - <PlainCh>0</PlainCh> - <Ropi>0</Ropi> - <Rwpi>0</Rwpi> - <wLevel>0</wLevel> - <uThumb>0</uThumb> - <uSurpInc>0</uSurpInc> - <uC99>0</uC99> - <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> - <v6Lto>0</v6Lto> - <v6WtE>0</v6WtE> - <v6Rtti>0</v6Rtti> - <VariousControls> - <MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls> - <Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U</Define> - <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> - </VariousControls> - </Cads> - <Aads> - <interw>1</interw> - <Ropi>0</Ropi> - <Rwpi>0</Rwpi> - <thumb>1</thumb> - <SplitLS>0</SplitLS> - <SwStkChk>0</SwStkChk> - <NoWarn>0</NoWarn> - <uSurpInc>0</uSurpInc> - <useXO>0</useXO> - <uClangAs>0</uClangAs> - <VariousControls> - <MiscControls>--cpreproc</MiscControls> - <Define>ARM_MATH_ARMV8MML __CC_ARM</Define> - <Undefine></Undefine> - <IncludePath></IncludePath> - </VariousControls> - </Aads> - <LDads> - <umfTarg>0</umfTarg> - <Ropi>0</Ropi> - <Rwpi>0</Rwpi> - <noStLib>0</noStLib> - <RepFail>1</RepFail> - <useFile>0</useFile> - <TextAddressRange>0x00000000</TextAddressRange> - <DataAddressRange>0x20000000</DataAddressRange> - <pXoBase></pXoBase> - <ScatterFile></ScatterFile> - <IncludeLibs></IncludeLibs> - <IncludeLibsPath></IncludeLibsPath> - <Misc></Misc> - <LinkerInputFile></LinkerInputFile> - <DisabledWarnings></DisabledWarnings> - </LDads> - </TargetArmAds> - </TargetOption> - <Groups> - <Group> - <GroupName>Libraries</GroupName> - <Files> - <File> - <FileName>arm_math.lib</FileName> - <FileType>4</FileType> - <FilePath>.\Lib\arm_math.lib</FilePath> - </File> - <File> - <FileName>arm_ref.lib</FileName> - <FileType>4</FileType> - <FilePath>.\Lib\arm_ref.lib</FilePath> - </File> - </Files> - </Group> - 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<StartAddress>0x200000</StartAddress> - <Size>0x200000</Size> - </OCR_RVCT5> - <OCR_RVCT6> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT6> - <OCR_RVCT7> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT7> - <OCR_RVCT8> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </OCR_RVCT8> - <OCR_RVCT9> - <Type>0</Type> - <StartAddress>0x20000000</StartAddress> - <Size>0x20000</Size> - </OCR_RVCT9> - <OCR_RVCT10> - <Type>0</Type> - <StartAddress>0x20200000</StartAddress> - <Size>0x20000</Size> - </OCR_RVCT10> - </OnChipMemories> - <RvctStartVector></RvctStartVector> - </ArmAdsMisc> - <Cads> - <interw>1</interw> - <Optim>1</Optim> + <Optim>2</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> <Ropi>0</Ropi> <Rwpi>0</Rwpi> - <wLevel>0</wLevel> + <wLevel>3</wLevel> <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>0</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> + <v6Lang>3</v6Lang> + <v6LangP>3</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> <v6Lto>0</v6Lto> <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> <VariousControls> - <MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls> - <Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U</Define> + <MiscControls>-fhonor-nans</MiscControls> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Cads> <Aads> @@ -11287,10 +9640,10 @@ <NoWarn>0</NoWarn> <uSurpInc>0</uSurpInc> <useXO>0</useXO> - <uClangAs>0</uClangAs> + <uClangAs>1</uClangAs> <VariousControls> - <MiscControls>--cpreproc</MiscControls> - <Define>ARM_MATH_ARMV8MML __CC_ARM</Define> + <MiscControls></MiscControls> + <Define></Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -11305,7 +9658,7 @@ <TextAddressRange>0x00000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> - <ScatterFile></ScatterFile> + <ScatterFile>..\..\Common\platform\ARMCLANG\armcc6_arm.sct</ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> <Misc></Misc> diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvoptx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvoptx new file mode 100644 index 0000000..770e9c5 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvoptx @@ -0,0 +1,3068 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>cortexM0l</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\cortexM0l\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFM.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFM</Key> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"..\cortexM0l_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>cortexM3l</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\cortexM3l\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFM.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFM</Key> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"..\cortexM3l_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>cortexM4l</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\cortexM4l\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFM.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFM</Key> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4l_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>cortexM4lf</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\cortexM4lf\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFM.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFM</Key> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>cortexM7l</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\cortexM7l\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFM.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFM</Key> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7l_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>cortexM7lfsp</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\cortexM7lfsp\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFM.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFM</Key> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfsp_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>cortexM7lfdp</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\cortexM7lfdp\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFM.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFM</Key> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfdp_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMv8MBLl</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\ARMv8MBLl\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>15</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFMv8M.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFMv8M</Key> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2V8M</Key> + <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMv8MMLl</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\ARMv8MMLl\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>15</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFMv8M.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFMv8M</Key> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2V8M</Key> + <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMv8MMLlfsp</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\ARMv8MMLlfsp\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>15</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFMv8M.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFMv8M</Key> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2V8M</Key> + <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMv8MMLld</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\IntermediateFiles\ARMv8MMLld\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>15</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile>..\..\Common\JTest\jtest_FVP.ini</tIfile> + <pMon>BIN\DbgFMv8M.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DbgFMv8M</Key> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1"</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2V8M</Key> + <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMv8MMLldfsp</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + 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<FileName>copy_tests.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\support_tests\copy_tests.c</FilePath> + </File> + <File> + <FileName>support_test_common_data.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\support_tests\support_test_common_data.c</FilePath> + </File> + <File> + <FileName>support_test_group.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\support_tests\support_test_group.c</FilePath> + </File> + <File> + <FileName>fill_tests.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\support_tests\fill_tests.c</FilePath> + </File> + <File> + <FileName>x_to_y_tests.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\support_tests\x_to_y_tests.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Intrinsics</GroupName> + <Files> + <File> + <FileName>intrinsics_tests.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\intrinsics_tests\intrinsics_tests.c</FilePath> + </File> + <File> + <FileName>intrinsics_tests_common_data.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>MathHelper</GroupName> + <Files> + <File> + <FileName>math_helper.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Common\src\math_helper.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> + + <RTE> + <apis/> + <components/> + <files/> + </RTE> + +</Project> diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt deleted file mode 100644 index 79e96c4..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt +++ /dev/null @@ -1,163 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt deleted file mode 100644 index 8ff1d62..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt deleted file mode 100644 index e6f8798..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt deleted file mode 100644 index 5c562f2..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt deleted file mode 100644 index de6a271..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt new file mode 100644 index 0000000..d9cb90a --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt new file mode 100644 index 0000000..9c3cfc2 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt new file mode 100644 index 0000000..011260a --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt new file mode 100644 index 0000000..2a0a82a --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt new file mode 100644 index 0000000..4140d9b --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx index 48cafe1..79f27f0 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx @@ -101,7 +101,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -138,7 +140,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"..\cortexM0l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -185,6 +187,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -268,7 +274,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -285,7 +293,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"..\cortexM3l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -332,6 +340,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -415,7 +427,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -432,7 +446,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -479,6 +493,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -562,7 +580,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -599,7 +619,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -646,6 +666,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -729,7 +753,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -766,7 +792,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7l_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -813,6 +839,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -896,7 +926,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -933,7 +965,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfsp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -980,6 +1012,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1063,7 +1099,9 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> - <nTsel>4</nTsel> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>5</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -1080,7 +1118,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFM</Key> - <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name> + <Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfdp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1127,6 +1165,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1210,6 +1252,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1242,7 +1286,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1289,6 +1333,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1372,6 +1420,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1389,7 +1439,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1436,6 +1486,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1519,6 +1573,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1551,7 +1607,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_FP_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1598,141 +1654,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> - </TargetOption> - </Target> - - <Target> - <TargetName>ARMv8MMLlfdp.DoNotUse</TargetName> - <ToolsetNumber>0x3</ToolsetNumber> - <ToolsetName>ARM-GNU</ToolsetName> - <TargetOption> - <CLKARM>12000000</CLKARM> - <OPTTT> - <gFlags>0</gFlags> - <BeepAtEnd>1</BeepAtEnd> - <RunSim>1</RunSim> - <RunTarget>0</RunTarget> - <RunAbUc>0</RunAbUc> - </OPTTT> - <OPTHX> - <HexSelection>1</HexSelection> - <FlashByte>65535</FlashByte> - <HexRangeLowAddress>0</HexRangeLowAddress> - <HexRangeHighAddress>0</HexRangeHighAddress> - <HexOffset>0</HexOffset> - </OPTHX> - <OPTLEX> - <PageWidth>120</PageWidth> - <PageLength>65</PageLength> - <TabStop>8</TabStop> - <ListingPath>.\IntermediateFiles\ARMv8MMLlfdp\</ListingPath> - </OPTLEX> - <ListingPage> - <CreateCListing>1</CreateCListing> - <CreateAListing>1</CreateAListing> - <CreateLListing>1</CreateLListing> - <CreateIListing>0</CreateIListing> - <AsmCond>1</AsmCond> - <AsmSymb>1</AsmSymb> - <AsmXref>0</AsmXref> - <CCond>1</CCond> - <CCode>0</CCode> - <CListInc>0</CListInc> - <CSymb>0</CSymb> - <LinkerCodeListing>0</LinkerCodeListing> - </ListingPage> - <OPTXL> - <LMap>1</LMap> - <LComments>1</LComments> - <LGenerateSymbols>1</LGenerateSymbols> - <LLibSym>1</LLibSym> - <LLines>1</LLines> - <LLocSym>1</LLocSym> - <LPubSym>1</LPubSym> - <LXref>0</LXref> - <LExpSel>0</LExpSel> - </OPTXL> - <OPTFL> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <IsCurrentTarget>0</IsCurrentTarget> - </OPTFL> - <CpuCode>7</CpuCode> - <DebugOpt> - <uSim>1</uSim> - <uTrg>0</uTrg> - <sLdApp>1</sLdApp> - <sGomain>1</sGomain> - <sRbreak>1</sRbreak> - <sRwatch>1</sRwatch> - <sRmem>1</sRmem> - <sRfunc>1</sRfunc> - <sRbox>1</sRbox> - <tLdApp>1</tLdApp> - <tGomain>0</tGomain> - <tRbreak>1</tRbreak> - <tRwatch>1</tRwatch> - <tRmem>1</tRmem> - <tRfunc>0</tRfunc> - <tRbox>1</tRbox> - <tRtrace>1</tRtrace> - <sRSysVw>1</sRSysVw> - <tRSysVw>1</tRSysVw> - <sRunDeb>0</sRunDeb> - <sLrtime>0</sLrtime> - <bEvRecOn>1</bEvRecOn> - <nTsel>-1</nTsel> - <sDll></sDll> - <sDllPa></sDllPa> - <sDlgDll></sDlgDll> - <sDlgPa></sDlgPa> - <sIfile></sIfile> - <tDll></tDll> - <tDllPa></tDllPa> - <tDlgDll></tDlgDll> - <tDlgPa></tDlgPa> - <tIfile></tIfile> - <pMon></pMon> - </DebugOpt> - <Breakpoint/> - <Tracepoint> - <THDelay>0</THDelay> - </Tracepoint> - <DebugFlag> - <trace>0</trace> - <periodic>0</periodic> - <aLwin>0</aLwin> - <aCover>0</aCover> - <aSer1>0</aSer1> - <aSer2>0</aSer2> - <aPa>0</aPa> - <viewmode>0</viewmode> - <vrSel>0</vrSel> - <aSym>0</aSym> - <aTbox>0</aTbox> - <AscS1>0</AscS1> - <AscS2>0</AscS2> - <AscS3>0</AscS3> - <aSer3>0</aSer3> - <eProf>0</eProf> - <aLa>0</aLa> - <aPa1>0</aPa1> - <AscS4>0</AscS4> - <aSer4>0</aSer4> - <StkLoc>0</StkLoc> - <TrcWin>0</TrcWin> - <newCpu>0</newCpu> - <uProt>0</uProt> - </DebugFlag> - <LintExecutable></LintExecutable> - <LintConfigFile></LintConfigFile> - <bLintAuto>0</bLintAuto> - <bAutoGenD>0</bAutoGenD> - <LntExFlags>0</LntExFlags> - <pMisraName></pMisraName> - <pszMrule></pszMrule> - <pSingCmds></pSingCmds> - <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1816,6 +1741,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -1848,7 +1775,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -1895,6 +1822,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> @@ -1978,6 +1909,8 @@ <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> <nTsel>15</nTsel> <sDll></sDll> <sDllPa></sDllPa> @@ -2010,7 +1943,7 @@ <SetRegEntry> <Number>0</Number> <Key>DbgFMv8M</Key> - <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_config.txt" -MA</Name> + <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA"-Q 1"</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -2057,141 +1990,10 @@ <pszMrule></pszMrule> <pSingCmds></pSingCmds> <pMultCmds></pMultCmds> - </TargetOption> - </Target> - - <Target> - <TargetName>ARMv8MMLldfdp.DoNotUse</TargetName> - <ToolsetNumber>0x3</ToolsetNumber> - <ToolsetName>ARM-GNU</ToolsetName> - <TargetOption> - <CLKARM>12000000</CLKARM> - <OPTTT> - <gFlags>0</gFlags> - <BeepAtEnd>1</BeepAtEnd> - <RunSim>1</RunSim> - <RunTarget>0</RunTarget> - <RunAbUc>0</RunAbUc> - </OPTTT> - <OPTHX> - <HexSelection>1</HexSelection> - <FlashByte>65535</FlashByte> - <HexRangeLowAddress>0</HexRangeLowAddress> - <HexRangeHighAddress>0</HexRangeHighAddress> - <HexOffset>0</HexOffset> - </OPTHX> - <OPTLEX> - <PageWidth>120</PageWidth> - <PageLength>65</PageLength> - <TabStop>8</TabStop> - <ListingPath>.\IntermediateFiles\ARMv8MMLldfdp\</ListingPath> - </OPTLEX> - <ListingPage> - <CreateCListing>1</CreateCListing> - <CreateAListing>1</CreateAListing> - <CreateLListing>1</CreateLListing> - <CreateIListing>0</CreateIListing> - <AsmCond>1</AsmCond> - <AsmSymb>1</AsmSymb> - <AsmXref>0</AsmXref> - <CCond>1</CCond> - <CCode>0</CCode> - <CListInc>0</CListInc> - <CSymb>0</CSymb> - <LinkerCodeListing>0</LinkerCodeListing> - </ListingPage> - <OPTXL> - <LMap>1</LMap> - <LComments>1</LComments> - <LGenerateSymbols>1</LGenerateSymbols> - <LLibSym>1</LLibSym> - <LLines>1</LLines> - <LLocSym>1</LLocSym> - <LPubSym>1</LPubSym> - <LXref>0</LXref> - <LExpSel>0</LExpSel> - </OPTXL> - <OPTFL> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <IsCurrentTarget>0</IsCurrentTarget> - </OPTFL> - <CpuCode>7</CpuCode> - <DebugOpt> - <uSim>1</uSim> - <uTrg>0</uTrg> - <sLdApp>1</sLdApp> - <sGomain>1</sGomain> - <sRbreak>1</sRbreak> - <sRwatch>1</sRwatch> - <sRmem>1</sRmem> - <sRfunc>1</sRfunc> - <sRbox>1</sRbox> - <tLdApp>1</tLdApp> - <tGomain>0</tGomain> - <tRbreak>1</tRbreak> - <tRwatch>1</tRwatch> - <tRmem>1</tRmem> - <tRfunc>0</tRfunc> - <tRbox>1</tRbox> - <tRtrace>1</tRtrace> - <sRSysVw>1</sRSysVw> - <tRSysVw>1</tRSysVw> - <sRunDeb>0</sRunDeb> - <sLrtime>0</sLrtime> - <bEvRecOn>1</bEvRecOn> - <nTsel>-1</nTsel> - <sDll></sDll> - <sDllPa></sDllPa> - <sDlgDll></sDlgDll> - <sDlgPa></sDlgPa> - <sIfile></sIfile> - <tDll></tDll> - <tDllPa></tDllPa> - <tDlgDll></tDlgDll> - <tDlgPa></tDlgPa> - <tIfile></tIfile> - <pMon></pMon> - </DebugOpt> - <Breakpoint/> - <Tracepoint> - <THDelay>0</THDelay> - </Tracepoint> - <DebugFlag> - <trace>0</trace> - <periodic>0</periodic> - <aLwin>0</aLwin> - <aCover>0</aCover> - <aSer1>0</aSer1> - <aSer2>0</aSer2> - <aPa>0</aPa> - <viewmode>0</viewmode> - <vrSel>0</vrSel> - <aSym>0</aSym> - <aTbox>0</aTbox> - <AscS1>0</AscS1> - <AscS2>0</AscS2> - <AscS3>0</AscS3> - <aSer3>0</aSer3> - <eProf>0</eProf> - <aLa>0</aLa> - <aPa1>0</aPa1> - <AscS4>0</AscS4> - <aSer4>0</aSer4> - <StkLoc>0</StkLoc> - <TrcWin>0</TrcWin> - <newCpu>0</newCpu> - <uProt>0</uProt> - </DebugFlag> - <LintExecutable></LintExecutable> - <LintConfigFile></LintConfigFile> - <bLintAuto>0</bLintAuto> - <bAutoGenD>0</bAutoGenD> - <LntExFlags>0</LntExFlags> - <pMisraName></pMisraName> - <pszMrule></pszMrule> - <pSingCmds></pSingCmds> - <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> </TargetOption> </Target> diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx index 0b5c53b..7d12245 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx @@ -10,11 +10,12 @@ <TargetName>cortexM0l</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM0</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -131,7 +132,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -166,6 +167,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <OnChipMemories> @@ -238,9 +240,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls> - <Define>ARM_MATH_CM0</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -248,7 +250,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM0</Define> + <Define>ARMCM0</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -734,11 +736,12 @@ <TargetName>cortexM3l</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM3</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -855,7 +858,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -890,6 +893,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <OnChipMemories> @@ -962,9 +966,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls> - <Define>ARM_MATH_CM3</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -972,7 +976,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM3</Define> + <Define>ARMCM3</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -1458,11 +1462,12 @@ <TargetName>cortexM4l</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM4</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -1579,7 +1584,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -1614,6 +1619,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <OnChipMemories> @@ -1686,9 +1692,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls> - <Define>ARM_MATH_CM4</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -1696,7 +1702,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM4</Define> + <Define>ARMCM4</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -2182,11 +2188,12 @@ <TargetName>cortexM4lf</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM4_FP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -2303,7 +2310,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -2338,6 +2345,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <OnChipMemories> @@ -2410,9 +2418,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls> - <Define>ARM_MATH_CM4 __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -2420,7 +2428,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM4</Define> + <Define>ARMCM4</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -2906,11 +2914,12 @@ <TargetName>cortexM7l</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM7</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -3027,7 +3036,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -3062,6 +3071,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <OnChipMemories> @@ -3134,9 +3144,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls> - <Define>ARM_MATH_CM7</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -3144,7 +3154,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM7</Define> + <Define>ARMCM7</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -3630,11 +3640,12 @@ <TargetName>cortexM7lfsp</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM7_SP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -3751,7 +3762,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -3786,6 +3797,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <OnChipMemories> @@ -3858,9 +3870,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls> - <Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -3868,7 +3880,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM7</Define> + <Define>ARMCM7</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -4354,11 +4366,12 @@ <TargetName>cortexM7lfdp</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMCM7_DP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -4475,7 +4488,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -4510,6 +4523,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>3</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <OnChipMemories> @@ -4582,9 +4596,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv5-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls> - <Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -4592,7 +4606,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_CM7</Define> + <Define>ARMCM7</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -5078,11 +5092,12 @@ <TargetName>ARMv8MBLl</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MBL</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -5199,7 +5214,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -5234,6 +5249,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <OnChipMemories> @@ -5306,9 +5322,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.base</MiscControls> - <Define>ARM_MATH_ARMV8MBL</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -5316,7 +5332,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_ARMV8MBL</Define> + <Define>ARMv8MBL</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -5802,11 +5818,12 @@ <TargetName>ARMv8MMLl</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -5923,7 +5940,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -5958,6 +5975,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <OnChipMemories> @@ -6030,9 +6048,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main</MiscControls> - <Define>ARM_MATH_ARMV8MML</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -6040,7 +6058,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_ARMV8MML</Define> + <Define>ARMv8MML</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -6526,11 +6544,12 @@ <TargetName>ARMv8MMLlfsp</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML_SP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -6647,7 +6666,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -6682,6 +6701,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <OnChipMemories> @@ -6754,9 +6774,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls> - <Define>ARM_MATH_ARMV8MML __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -6764,7 +6784,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_ARMV8MML</Define> + <Define>ARMv8MML</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -7247,738 +7267,15 @@ </Groups> </Target> <Target> - <TargetName>ARMv8MMLlfdp.DoNotUse</TargetName> - <ToolsetNumber>0x3</ToolsetNumber> - <ToolsetName>ARM-GNU</ToolsetName> - <TargetOption> - <TargetCommonOption> - <Device>ARMv8MML_DP</Device> - <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> - <PackURL>http://www.keil.com/pack/</PackURL> - <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(DFPU) TZ CLOCK(12000000) ESEL ELITTLE</Cpu> - <FlashUtilSpec></FlashUtilSpec> - <StartupFile></StartupFile> - <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll> - <DeviceId>0</DeviceId> - <RegisterFile>$$Device:ARMv8MML_DP$Device\ARM\ARMv8MML\Include\ARMv8MML_DP.h</RegisterFile> - <MemoryEnv></MemoryEnv> - <Cmp></Cmp> - <Asm></Asm> - <Linker></Linker> - <OHString></OHString> - <InfinionOptionDll></InfinionOptionDll> - <SLE66CMisc></SLE66CMisc> - <SLE66AMisc></SLE66AMisc> - <SLE66LinkerMisc></SLE66LinkerMisc> - <SFDFile>$$Device:ARMv8MML_DP$Device\ARM\SVD\ARMv8MML.svd</SFDFile> - <bCustSvd>0</bCustSvd> - <UseEnv>0</UseEnv> - <BinPath></BinPath> - <IncludePath></IncludePath> - <LibPath></LibPath> - <RegisterFilePath></RegisterFilePath> - <DBRegisterFilePath></DBRegisterFilePath> - <TargetStatus> - <Error>0</Error> - <ExitCodeStop>0</ExitCodeStop> - <ButtonStop>0</ButtonStop> - <NotGenerated>0</NotGenerated> - <InvalidFlash>1</InvalidFlash> - </TargetStatus> - <OutputDirectory>.\IntermediateFiles\ARMv8MMLlfdp\</OutputDirectory> - <OutputName>DspLibTest_FVP</OutputName> - <CreateExecutable>1</CreateExecutable> - <CreateLib>0</CreateLib> - <CreateHexFile>0</CreateHexFile> - <DebugInformation>1</DebugInformation> - <BrowseInformation>1</BrowseInformation> - <ListingPath>.\IntermediateFiles\ARMv8MMLlfdp\</ListingPath> - <HexFormatSelection>1</HexFormatSelection> - <Merge32K>0</Merge32K> - <CreateBatchFile>0</CreateBatchFile> - <BeforeCompile> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopU1X>0</nStopU1X> - <nStopU2X>0</nStopU2X> - </BeforeCompile> - <BeforeMake> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopB1X>0</nStopB1X> - <nStopB2X>0</nStopB2X> - </BeforeMake> - <AfterMake> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopA1X>0</nStopA1X> - <nStopA2X>0</nStopA2X> - </AfterMake> - <SelectedForBatchBuild>0</SelectedForBatchBuild> - <SVCSIdString></SVCSIdString> - </TargetCommonOption> - <CommonProperty> - <UseCPPCompiler>0</UseCPPCompiler> - <RVCTCodeConst>0</RVCTCodeConst> - <RVCTZI>0</RVCTZI> - <RVCTOtherData>0</RVCTOtherData> - <ModuleSelection>0</ModuleSelection> - <IncludeInBuild>1</IncludeInBuild> - <AlwaysBuild>0</AlwaysBuild> - <GenerateAssemblyFile>0</GenerateAssemblyFile> - <AssembleAssemblyFile>0</AssembleAssemblyFile> - <PublicsOnly>0</PublicsOnly> - <StopOnExitCode>3</StopOnExitCode> - <CustomArgument></CustomArgument> - <IncludeLibraryModules></IncludeLibraryModules> - <ComprImg>1</ComprImg> - </CommonProperty> - <DllOption> - <SimDllName></SimDllName> - <SimDllArguments></SimDllArguments> - <SimDlgDll></SimDlgDll> - <SimDlgDllArguments></SimDlgDllArguments> - <TargetDllName>SARMV8M.DLL</TargetDllName> - <TargetDllArguments> -MPU</TargetDllArguments> - <TargetDlgDll>TCM.DLL</TargetDlgDll> - <TargetDlgDllArguments>-pV8MML</TargetDlgDllArguments> - </DllOption> - <DebugOption> - <OPTHX> - <HexSelection>1</HexSelection> - <HexRangeLowAddress>0</HexRangeLowAddress> - <HexRangeHighAddress>0</HexRangeHighAddress> - <HexOffset>0</HexOffset> - <Oh166RecLen>16</Oh166RecLen> - </OPTHX> - </DebugOption> - <Utilities> - <Flash1> - <UseTargetDll>1</UseTargetDll> - <UseExternalTool>0</UseExternalTool> - <RunIndependent>0</RunIndependent> - <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> - <DriverSelection>4096</DriverSelection> - </Flash1> - <bUseTDR>1</bUseTDR> - <Flash2>BIN\UL2V8M.DLL</Flash2> - <Flash3></Flash3> - <Flash4></Flash4> - <pFcarmOut></pFcarmOut> - <pFcarmGrp></pFcarmGrp> - <pFcArmRoot></pFcArmRoot> - <FcArmLst>0</FcArmLst> - </Utilities> - <TargetArm> - <ArmMisc> - <asLst>0</asLst> - <asHll>1</asHll> - <asAsm>1</asAsm> - <asMacX>1</asMacX> - <asSyms>1</asSyms> - <asFals>1</asFals> - <asDbgD>1</asDbgD> - <asForm>1</asForm> - <ldLst>0</ldLst> - <ldmm>1</ldmm> - <ldXref>1</ldXref> - <BigEnd>0</BigEnd> - <GCPUTYP>"ARMV8MML"</GCPUTYP> - <mOS>0</mOS> - <uocRom>0</uocRom> - <uocRam>0</uocRam> - <hadIROM>1</hadIROM> - <hadIRAM>1</hadIRAM> - <hadXRAM>0</hadXRAM> - <uocXRam>0</uocXRam> - <RvdsVP>3</RvdsVP> - <hadIRAM2>1</hadIRAM2> - <hadIROM2>1</hadIROM2> - <OnChipMemories> - <Ocm1> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm1> - <Ocm2> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm2> - <Ocm3> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm3> - <Ocm4> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm4> - <Ocm5> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm5> - <Ocm6> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm6> - <IRAM> - <Type>0</Type> - <StartAddress>0x20000000</StartAddress> - <Size>0x20000</Size> - </IRAM> - <IROM> - <Type>1</Type> - <StartAddress>0x0</StartAddress> - <Size>0x200000</Size> - </IROM> - <XRAM> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - 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</File> - <File> - <FileName>x_to_y_tests.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\support_tests\x_to_y_tests.c</FilePath> - </File> - </Files> - </Group> - <Group> - <GroupName>Intrinsics</GroupName> - <Files> - <File> - <FileName>intrinsics_tests.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\intrinsics_tests\intrinsics_tests.c</FilePath> - </File> - <File> - <FileName>intrinsics_tests_common_data.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c</FilePath> - </File> - </Files> - </Group> - <Group> - <GroupName>MathHelper</GroupName> - <Files> - <File> - <FileName>math_helper.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\math_helper.c</FilePath> - </File> - </Files> - </Group> - </Groups> - </Target> - <Target> <TargetName>ARMv8MMLld</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML_DSP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -8095,7 +7392,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -8130,6 +7427,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <OnChipMemories> @@ -8202,9 +7500,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp</MiscControls> - <Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -8212,7 +7510,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_ARMV8MML</Define> + <Define>ARMv8MML</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -8698,11 +7996,12 @@ <TargetName>ARMv8MMLldfsp</TargetName> <ToolsetNumber>0x3</ToolsetNumber> <ToolsetName>ARM-GNU</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>ARMv8MML_DSP_SP</Device> <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> + <PackID>ARM.CMSIS.5.5.0-dev52</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -8819,7 +8118,7 @@ <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> + <Capability>0</Capability> <DriverSelection>4096</DriverSelection> </Flash1> <bUseTDR>1</bUseTDR> @@ -8854,6 +8153,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>2</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <OnChipMemories> @@ -8926,9 +8226,9 @@ <uThumb>1</uThumb> <VariousControls> <MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls> - <Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U</Define> + <Define></Define> <Undefine></Undefine> - <IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> + <IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath> </VariousControls> </Carm> <Aarm> @@ -8936,7 +8236,7 @@ <interw>0</interw> <VariousControls> <MiscControls></MiscControls> - <Define>ARM_MATH_ARMV8MML</Define> + <Define>ARMv8MML</Define> <Undefine></Undefine> <IncludePath></IncludePath> </VariousControls> @@ -9418,730 +8718,6 @@ </Group> </Groups> </Target> - <Target> - <TargetName>ARMv8MMLldfdp.DoNotUse</TargetName> - <ToolsetNumber>0x3</ToolsetNumber> - <ToolsetName>ARM-GNU</ToolsetName> - <TargetOption> - <TargetCommonOption> - <Device>ARMv8MML_DSP_DP</Device> - <Vendor>ARM</Vendor> - <PackID>ARM.CMSIS.5.0.1-dev6</PackID> - <PackURL>http://www.keil.com/pack/</PackURL> - <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(DFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu> - <FlashUtilSpec></FlashUtilSpec> - <StartupFile></StartupFile> - <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll> - <DeviceId>0</DeviceId> - <RegisterFile>$$Device:ARMv8MML_DSP_DP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP_DP.h</RegisterFile> - <MemoryEnv></MemoryEnv> - <Cmp></Cmp> - <Asm></Asm> - <Linker></Linker> - <OHString></OHString> - <InfinionOptionDll></InfinionOptionDll> - <SLE66CMisc></SLE66CMisc> - <SLE66AMisc></SLE66AMisc> - <SLE66LinkerMisc></SLE66LinkerMisc> - <SFDFile>$$Device:ARMv8MML_DSP_DP$Device\ARM\SVD\ARMv8MML.svd</SFDFile> - <bCustSvd>0</bCustSvd> - <UseEnv>0</UseEnv> - <BinPath></BinPath> - <IncludePath></IncludePath> - <LibPath></LibPath> - <RegisterFilePath></RegisterFilePath> - <DBRegisterFilePath></DBRegisterFilePath> - <TargetStatus> - <Error>0</Error> - <ExitCodeStop>0</ExitCodeStop> - <ButtonStop>0</ButtonStop> - <NotGenerated>0</NotGenerated> - <InvalidFlash>1</InvalidFlash> - </TargetStatus> - <OutputDirectory>.\IntermediateFiles\ARMv8MMLldfdp\</OutputDirectory> - <OutputName>DspLibTest_FVP</OutputName> - <CreateExecutable>1</CreateExecutable> - <CreateLib>0</CreateLib> - <CreateHexFile>0</CreateHexFile> - <DebugInformation>1</DebugInformation> - <BrowseInformation>1</BrowseInformation> - <ListingPath>.\IntermediateFiles\ARMv8MMLldfdp\</ListingPath> - <HexFormatSelection>1</HexFormatSelection> - <Merge32K>0</Merge32K> - <CreateBatchFile>0</CreateBatchFile> - <BeforeCompile> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopU1X>0</nStopU1X> - <nStopU2X>0</nStopU2X> - </BeforeCompile> - <BeforeMake> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopB1X>0</nStopB1X> - <nStopB2X>0</nStopB2X> - </BeforeMake> - <AfterMake> - <RunUserProg1>0</RunUserProg1> - <RunUserProg2>0</RunUserProg2> - <UserProg1Name></UserProg1Name> - <UserProg2Name></UserProg2Name> - <UserProg1Dos16Mode>0</UserProg1Dos16Mode> - <UserProg2Dos16Mode>0</UserProg2Dos16Mode> - <nStopA1X>0</nStopA1X> - <nStopA2X>0</nStopA2X> - </AfterMake> - <SelectedForBatchBuild>0</SelectedForBatchBuild> - <SVCSIdString></SVCSIdString> - </TargetCommonOption> - <CommonProperty> - <UseCPPCompiler>0</UseCPPCompiler> - <RVCTCodeConst>0</RVCTCodeConst> - <RVCTZI>0</RVCTZI> - <RVCTOtherData>0</RVCTOtherData> - <ModuleSelection>0</ModuleSelection> - <IncludeInBuild>1</IncludeInBuild> - <AlwaysBuild>0</AlwaysBuild> - <GenerateAssemblyFile>0</GenerateAssemblyFile> - <AssembleAssemblyFile>0</AssembleAssemblyFile> - <PublicsOnly>0</PublicsOnly> - <StopOnExitCode>3</StopOnExitCode> - <CustomArgument></CustomArgument> - <IncludeLibraryModules></IncludeLibraryModules> - <ComprImg>1</ComprImg> - </CommonProperty> - <DllOption> - <SimDllName></SimDllName> - <SimDllArguments></SimDllArguments> - <SimDlgDll></SimDlgDll> - <SimDlgDllArguments></SimDlgDllArguments> - <TargetDllName>SARMV8M.DLL</TargetDllName> - <TargetDllArguments> -MPU</TargetDllArguments> - <TargetDlgDll>TCM.DLL</TargetDlgDll> - <TargetDlgDllArguments>-pV8MML</TargetDlgDllArguments> - </DllOption> - <DebugOption> - <OPTHX> - <HexSelection>1</HexSelection> - <HexRangeLowAddress>0</HexRangeLowAddress> - <HexRangeHighAddress>0</HexRangeHighAddress> - <HexOffset>0</HexOffset> - <Oh166RecLen>16</Oh166RecLen> - </OPTHX> - </DebugOption> - <Utilities> - <Flash1> - <UseTargetDll>1</UseTargetDll> - <UseExternalTool>0</UseExternalTool> - <RunIndependent>0</RunIndependent> - <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> - <Capability>1</Capability> - <DriverSelection>4096</DriverSelection> - </Flash1> - <bUseTDR>1</bUseTDR> - <Flash2>BIN\UL2V8M.DLL</Flash2> - <Flash3></Flash3> - <Flash4></Flash4> - <pFcarmOut></pFcarmOut> - <pFcarmGrp></pFcarmGrp> - <pFcArmRoot></pFcArmRoot> - <FcArmLst>0</FcArmLst> - </Utilities> - <TargetArm> - <ArmMisc> - <asLst>0</asLst> - <asHll>1</asHll> - <asAsm>1</asAsm> - <asMacX>1</asMacX> - <asSyms>1</asSyms> - <asFals>1</asFals> - <asDbgD>1</asDbgD> - <asForm>1</asForm> - <ldLst>0</ldLst> - <ldmm>1</ldmm> - <ldXref>1</ldXref> - <BigEnd>0</BigEnd> - <GCPUTYP>"ARMV8MML"</GCPUTYP> - <mOS>0</mOS> - <uocRom>0</uocRom> - <uocRam>0</uocRam> - <hadIROM>1</hadIROM> - <hadIRAM>1</hadIRAM> - <hadXRAM>0</hadXRAM> - <uocXRam>0</uocXRam> - <RvdsVP>3</RvdsVP> - <hadIRAM2>1</hadIRAM2> - <hadIROM2>1</hadIROM2> - <OnChipMemories> - <Ocm1> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm1> - <Ocm2> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm2> - <Ocm3> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm3> - <Ocm4> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm4> - <Ocm5> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm5> - <Ocm6> - <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> - </Ocm6> - <IRAM> - <Type>0</Type> - <StartAddress>0x20000000</StartAddress> - <Size>0x20000</Size> - </IRAM> - <IROM> - <Type>1</Type> - <StartAddress>0x0</StartAddress> - <Size>0x200000</Size> - </IROM> - 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</File> - <File> - <FileName>x_to_y_tests.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\support_tests\x_to_y_tests.c</FilePath> - </File> - </Files> - </Group> - <Group> - <GroupName>Intrinsics</GroupName> - <Files> - <File> - <FileName>intrinsics_tests.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\intrinsics_tests\intrinsics_tests.c</FilePath> - </File> - <File> - <FileName>intrinsics_tests_common_data.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c</FilePath> - </File> - </Files> - </Group> - <Group> - <GroupName>MathHelper</GroupName> - <Files> - <File> - <FileName>math_helper.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\Common\src\math_helper.c</FilePath> - </File> - </Files> - </Group> - </Groups> - </Target> </Targets> <RTE> diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt new file mode 100644 index 0000000..8e33c76 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt new file mode 100644 index 0000000..2caf254 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm3ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm3ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt new file mode 100644 index 0000000..1c9fece --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt new file mode 100644 index 0000000..eb832ed --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt new file mode 100644 index 0000000..4e591c9 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- |