From 96d6da4e252b06dcfdc041e7df23e86161c33007 Mon Sep 17 00:00:00 2001 From: rihab kouki Date: Tue, 28 Jul 2020 11:24:49 +0100 Subject: Official ARM version: v5.6.0 --- .../DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx | 382 +- .../DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx | 2039 +--- .../DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvoptx | 3068 ++++++ .../DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvprojx | 10151 +++++++++++++++++++ .../DspLibTest_FVP/ARMCLANG/Lib/.gitignore | 4 + .../DspLibTest_FVP/ARMCLANG/Logs/.gitignore | 4 + .../DspLibTest_FVP/ARMCM23_config.txt | 163 - .../DspLibTest_FVP/ARMCM33_DSP_FP_config.txt | 183 - .../DspLibTest_FVP/ARMCM33_DSP_config.txt | 183 - .../DspLibTest_FVP/ARMCM33_FP_config.txt | 183 - .../DspLibTest_FVP/ARMCM33_config.txt | 183 - .../DspLibTest_FVP/ARMv8MBLl_config.txt | 11 + .../DspLibTest_FVP/ARMv8MMLl_config.txt | 13 + .../DspLibTest_FVP/ARMv8MMLld_config.txt | 13 + .../DspLibTest_FVP/ARMv8MMLldfsp_config.txt | 13 + .../DspLibTest_FVP/ARMv8MMLlfsp_config.txt | 13 + .../DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx | 380 +- .../DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx | 1630 +-- .../DspLibTest_FVP/cortexM0l_config.txt | 8 + .../DspLibTest_FVP/cortexM3l_config.txt | 8 + .../DspLibTest_FVP/cortexM4l_config.txt | 9 + .../DspLibTest_FVP/cortexM4lf_config.txt | 9 + .../DspLibTest_FVP/cortexM7l_config.txt | 9 + .../DspLibTest_FVP/cortexM7lfdp_config.txt | 9 + .../DspLibTest_FVP/cortexM7lfsp_config.txt | 9 + 25 files changed, 13833 insertions(+), 4844 deletions(-) create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvoptx create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvprojx create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore delete mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt delete mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt delete mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt delete mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt delete mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt (limited to 'DSP/DSP_Lib_TestSuite/DspLibTest_FVP') diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx index 5145d60..fbd1ae9 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx @@ -101,7 +101,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -138,7 +140,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"../cortexM0l_config.txt" -MA"-Q 1" 0 @@ -185,6 +187,10 @@ + + + + @@ -268,7 +274,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -285,7 +293,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"../cortexM3l_config.txt" -MA"-Q 1" 0 @@ -332,6 +340,10 @@ + + + + @@ -415,7 +427,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -432,7 +446,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"../cortexM4l_config.txt" -MA"-Q 1" 0 @@ -479,6 +493,10 @@ + + + + @@ -562,7 +580,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -599,7 +619,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1" 0 @@ -646,6 +666,10 @@ + + + + @@ -729,7 +753,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -766,7 +792,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7l_config.txt" -MA"-Q 1" 0 @@ -813,6 +839,10 @@ + + + + @@ -896,7 +926,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -933,7 +965,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfsp_config.txt" -MA"-Q 1" 0 @@ -980,6 +1012,10 @@ + + + + @@ -1063,7 +1099,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -1080,7 +1118,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfdp_config.txt" -MA"-Q 1" 0 @@ -1127,6 +1165,10 @@ + + + + @@ -1210,6 +1252,8 @@ 0 0 1 + 0 + 0 15 @@ -1242,7 +1286,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1" 0 @@ -1289,6 +1333,10 @@ + + + + @@ -1372,6 +1420,8 @@ 0 0 1 + 0 + 0 15 @@ -1389,7 +1439,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1" 0 @@ -1436,6 +1486,10 @@ + + + + @@ -1519,6 +1573,8 @@ 0 0 1 + 0 + 0 15 @@ -1551,7 +1607,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_FP_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1" 0 @@ -1598,141 +1654,10 @@ - - - - - ARMv8MMLlfdp.DoNotUse - 0x4 - ARM-ADS - - 12000000 - - 0 - 1 - 1 - 0 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\IntermediateFiles\ARMv8MMLlfdp\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 0 - - 7 - - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - -1 - - - - - - - - - - - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - + + + + @@ -1816,6 +1741,8 @@ 0 0 1 + 0 + 0 15 @@ -1848,7 +1775,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1" 0 @@ -1895,6 +1822,10 @@ + + + + @@ -1978,6 +1909,8 @@ 0 0 1 + 0 + 0 15 @@ -2010,7 +1943,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA"-Q 1" 0 @@ -2057,141 +1990,10 @@ - - - - - ARMv8MMLldfdp.DoNotUse - 0x4 - ARM-ADS - - 12000000 - - 0 - 1 - 1 - 0 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\IntermediateFiles\ARMv8MMLldfdp\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 0 - - 7 - - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - -1 - - - - - - - - - - - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - + + + + @@ -2705,7 +2507,7 @@ 8 38 1 - 0 + 1 0 0 ..\..\Common\src\controller_tests\pid_reset_tests.c diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx index 7296f06..bc06615 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx @@ -10,11 +10,13 @@ cortexM0l 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 ARMCM0 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE @@ -131,7 +133,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -182,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -322,6 +325,7 @@ 0 0 0 + 0 0 0 0 @@ -332,9 +336,9 @@ 0 - ARM_MATH_CM0 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -349,8 +353,8 @@ 0 0 - --cpreproc --cpreproc_opts=-D,ARM_MATH_CM0 - ARM_MATH_CM0 + --cpreproc --cpreproc_opts=-D,ARMCM0 + @@ -365,7 +369,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCC\armcc5_arm.sct @@ -851,11 +855,12 @@ cortexM3l 0x4 ARM-ADS + 0 ARMCM3 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -911,8 +916,8 @@ 0 0 - python Scripts/get_ref_and_dsp_libs.py ARM M3l - python Scripts/get_ref_and_dsp_libs.py GCC M3l + + 0 0 0 @@ -972,7 +977,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -1023,6 +1028,7 @@ 0 0 0 + 0 0 0 8 @@ -1163,6 +1169,7 @@ 0 0 0 + 0 0 0 0 @@ -1173,9 +1180,9 @@ 0 - ARM_MATH_CM3 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -1190,8 +1197,8 @@ 0 0 - --cpreproc --cpreproc_opts=-D,ARM_MATH_CM3 - ARM_MATH_CM3 + --cpreproc --cpreproc_opts=-D,ARMCM3 + @@ -1206,7 +1213,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCC\armcc5_arm.sct @@ -1692,11 +1699,12 @@ cortexM4l 0x4 ARM-ADS + 0 ARMCM4 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE @@ -1752,8 +1760,8 @@ 0 0 - python Scripts/get_ref_and_dsp_libs.py ARM M4l - python Scripts/get_ref_and_dsp_libs.py GCC M4l + + 0 0 0 @@ -1813,7 +1821,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -1864,6 +1872,7 @@ 0 0 0 + 0 0 0 8 @@ -2004,6 +2013,7 @@ 0 0 0 + 0 0 0 0 @@ -2014,9 +2024,9 @@ 0 - ARM_MATH_CM4 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -2031,8 +2041,8 @@ 0 0 - --cpreproc --cpreproc_opts=-D,ARM_MATH_CM4 - ARM_MATH_CM4 + --cpreproc --cpreproc_opts=-D,ARMCM4 + @@ -2047,7 +2057,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCC\armcc5_arm.sct @@ -2533,11 +2543,12 @@ cortexM4lf 0x4 ARM-ADS + 0 ARMCM4_FP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE @@ -2593,8 +2604,8 @@ 0 0 - python Scripts/get_ref_and_dsp_libs.py ARM M4lf - python Scripts/get_ref_and_dsp_libs.py GCC M4lf + + 0 0 0 @@ -2654,7 +2665,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -2705,6 +2716,7 @@ 0 0 2 + 0 0 0 8 @@ -2845,6 +2857,7 @@ 0 0 0 + 0 0 0 0 @@ -2855,9 +2868,9 @@ 0 - ARM_MATH_CM4 __FPU_PRESENT=1U + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -2872,8 +2885,8 @@ 0 0 - --cpreproc --cpreproc_opts=-D,ARM_MATH_CM4 - ARM_MATH_CM4 + --cpreproc --cpreproc_opts=-D,ARMCM4 + @@ -2888,7 +2901,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCC\armcc5_arm.sct @@ -3374,11 +3387,12 @@ cortexM7l 0x4 ARM-ADS + 0 ARMCM7 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE @@ -3434,8 +3448,8 @@ 0 0 - python Scripts/get_ref_and_dsp_libs.py ARM M4l - python Scripts/get_ref_and_dsp_libs.py GCC M4l + + 0 0 0 @@ -3495,7 +3509,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -3546,6 +3560,7 @@ 0 0 0 + 0 0 0 8 @@ -3686,6 +3701,7 @@ 0 0 0 + 0 0 0 0 @@ -3696,9 +3712,9 @@ 0 - ARM_MATH_CM7 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -3713,8 +3729,8 @@ 0 0 - --cpreproc --cpreproc_opts=-D,ARM_MATH_CM7 - ARM_MATH_CM7 + --cpreproc --cpreproc_opts=-D,ARMCM7 + @@ -3729,7 +3745,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCC\armcc5_arm.sct @@ -4215,11 +4231,12 @@ cortexM7lfsp 0x4 ARM-ADS + 0 ARMCM7_SP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE @@ -4275,8 +4292,8 @@ 0 0 - python Scripts/get_ref_and_dsp_libs.py ARM M4lf - python Scripts/get_ref_and_dsp_libs.py GCC M4lf + + 0 0 0 @@ -4336,7 +4353,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -4387,6 +4404,7 @@ 0 0 2 + 0 0 0 8 @@ -4527,6 +4545,7 @@ 0 0 0 + 0 0 0 0 @@ -4537,9 +4556,9 @@ 0 - ARM_MATH_CM7 __FPU_PRESENT=1U + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -4554,8 +4573,8 @@ 0 0 - --cpreproc --cpreproc_opts=-D,ARM_MATH_CM7 - ARM_MATH_CM7 + --cpreproc --cpreproc_opts=-D,ARMCM7 + @@ -4570,7 +4589,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCC\armcc5_arm.sct @@ -5056,11 +5075,12 @@ cortexM7lfdp 0x4 ARM-ADS + 0 ARMCM7_DP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE @@ -5177,7 +5197,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -5228,6 +5248,7 @@ 0 0 3 + 0 0 0 8 @@ -5368,6 +5389,7 @@ 0 0 0 + 0 0 0 0 @@ -5378,9 +5400,9 @@ 0 - ARM_MATH_CM7 __FPU_PRESENT=1U + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -5395,8 +5417,8 @@ 0 0 - --cpreproc --cpreproc_opts=-D,ARM_MATH_CM7 - ARM_MATH_CM7 + --cpreproc --cpreproc_opts=-D,ARMCM7 + @@ -5411,7 +5433,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCC\armcc5_arm.sct @@ -5897,12 +5919,13 @@ ARMv8MBLl 0x4 ARM-ADS - 6060000::V6.6::.\ARMCLANG + 6110000::V6.11::.\ARMCLANG_6.11 + 1 ARMv8MBL ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE @@ -6019,7 +6042,7 @@ 0 0 1 - 1 + 0 4097 1 @@ -6045,7 +6068,7 @@ 1 1 0 - 1 + 0 1 0 0 @@ -6070,6 +6093,7 @@ 0 0 0 + 0 0 0 8 @@ -6197,32 +6221,33 @@ 1 - 1 + 2 0 0 - 0 + 1 0 0 0 0 0 - 0 + 3 0 0 0 + 0 0 - 0 - 0 - 0 - 0 + 3 + 3 + 1 + 1 0 0 0 -fhonor-nans - ARM_MATH_ARMV8MBL + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -6235,10 +6260,10 @@ 0 0 0 - 0 + 1 - --cpreproc - ARM_MATH_ARMV8MBL __CC_ARM + + ARMv8MBL @@ -6253,7 +6278,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCLANG\armcc6_arm.sct @@ -6740,11 +6765,12 @@ 0x4 ARM-ADS 6060000::V6.6::.\ARMCLANG + 1 ARMv8MML ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") TZ CLOCK(12000000) ESEL ELITTLE @@ -6861,7 +6887,7 @@ 0 0 1 - 1 + 0 4097 1 @@ -6912,6 +6938,7 @@ 0 0 0 + 0 1 1 8 @@ -7039,32 +7066,33 @@ 1 - 1 + 2 0 0 - 0 + 1 0 0 0 0 0 - 0 + 3 0 0 0 + 0 0 - 0 - 0 - 0 - 0 + 3 + 3 + 1 + 1 0 0 0 - -Xclang -target-feature -Xclang +t2xtpk -fhonor-nans - ARM_MATH_ARMV8MML + -fhonor-nans + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -7077,10 +7105,10 @@ 0 0 0 - 0 + 1 - --cpreproc - ARM_MATH_ARMV8MML __CC_ARM + + @@ -7095,7 +7123,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCLANG\armcc6_arm.sct @@ -7582,11 +7610,12 @@ 0x4 ARM-ADS 6060000::V6.6::.\ARMCLANG + 1 ARMv8MML_SP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) TZ CLOCK(12000000) ESEL ELITTLE @@ -7703,7 +7732,7 @@ 0 0 1 - 1 + 0 4097 1 @@ -7754,6 +7783,7 @@ 0 0 2 + 0 1 1 8 @@ -7881,32 +7911,33 @@ 1 - 1 + 2 0 0 - 0 + 1 0 0 0 0 0 - 0 + 3 0 0 0 + 0 0 - 0 - 0 - 0 - 0 + 3 + 3 + 1 + 1 0 0 0 - -Xclang -target-feature -Xclang +t2xtpk -fhonor-nans - ARM_MATH_ARMV8MML __FPU_PRESENT=1U + -fhonor-nans + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -7919,10 +7950,10 @@ 0 0 0 - 0 + 1 - --cpreproc - ARM_MATH_ARMV8MML __CC_ARM + + @@ -7937,7 +7968,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCLANG\armcc6_arm.sct @@ -8420,22 +8451,23 @@ - ARMv8MMLlfdp.DoNotUse + ARMv8MMLld 0x4 ARM-ADS 6060000::V6.6::.\ARMCLANG + 1 - ARMv8MML_DP + ARMv8MML_DSP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(DFPU) TZ CLOCK(12000000) ESEL ELITTLE + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") DSP TZ CLOCK(12000000) ESEL ELITTLE UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) 0 - $$Device:ARMv8MML_DP$Device\ARM\ARMv8MML\Include\ARMv8MML_DP.h + $$Device:ARMv8MML_DSP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP.h @@ -8445,7 +8477,7 @@ - $$Device:ARMv8MML_DP$Device\ARM\SVD\ARMv8MML.svd + $$Device:ARMv8MML_DSP$Device\ARM\SVD\ARMv8MML.svd 0 0 @@ -8460,14 +8492,14 @@ 0 1 - .\IntermediateFiles\ARMv8MMLlfdp\ + .\IntermediateFiles\ARMv8MMLld\ DspLibTest_FVP 1 0 0 1 1 - .\IntermediateFiles\ARMv8MMLlfdp\ + .\IntermediateFiles\ARMv8MMLld\ 1 0 0 @@ -8544,8 +8576,8 @@ 1 0 0 - 0 - 1 + 1 + 0 4097 1 @@ -8595,7 +8627,8 @@ 1 0 0 - 3 + 0 + 0 1 1 8 @@ -8723,32 +8756,33 @@ 1 - 1 + 2 0 0 - 0 + 1 0 0 0 0 0 - 0 + 3 0 0 0 + 0 0 - 0 - 0 - 0 - 0 + 3 + 3 + 1 + 1 0 0 0 - -Xclang -target-feature -Xclang +t2xtpk -fhonor-nans - ARM_MATH_ARMV8MML __FPU_PRESENT=1U + -fhonor-nans + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -8761,10 +8795,10 @@ 0 0 0 - 0 + 1 - --cpreproc - ARM_MATH_ARMV8MML __CC_ARM + + @@ -8779,7 +8813,7 @@ 0x00000000 0x20000000 - + ..\..\Common\platform\ARMCLANG\armcc6_arm.sct @@ -9262,22 +9296,23 @@ - ARMv8MMLld + ARMv8MMLldfsp 0x4 ARM-ADS - 6060000::V6.6::.\ARMCLANG + 6110000::V6.11::.\ARMCLANG 6.11 + 1 - ARMv8MML_DSP + ARMv8MML_DSP_SP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") DSP TZ CLOCK(12000000) ESEL ELITTLE + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) 0 - $$Device:ARMv8MML_DSP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP.h + $$Device:ARMv8MML_DSP_SP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP_SP.h @@ -9287,7 +9322,7 @@ - $$Device:ARMv8MML_DSP$Device\ARM\SVD\ARMv8MML.svd + $$Device:ARMv8MML_DSP_SP$Device\ARM\SVD\ARMv8MML.svd 0 0 @@ -9302,14 +9337,14 @@ 0 1 - .\IntermediateFiles\ARMv8MMLld\ + .\IntermediateFiles\ARMv8MMLldfsp\ DspLibTest_FVP 1 0 0 1 1 - .\IntermediateFiles\ARMv8MMLld\ + .\IntermediateFiles\ARMv8MMLldfsp\ 1 0 0 @@ -9387,12 +9422,12 @@ 0 0 1 - 1 + 0 4097 1 BIN\UL2V8M.DLL - + "" () @@ -9437,7 +9472,8 @@ 1 0 0 - 0 + 2 + 0 1 1 8 @@ -9565,32 +9601,33 @@ 1 - 1 + 2 0 0 - 0 + 1 0 0 0 0 0 - 0 + 3 0 0 0 + 0 0 - 0 - 0 - 0 - 0 + 3 + 3 + 1 + 1 0 0 0 - -Xclang -target-feature -Xclang +t2xtpk -fhonor-nans - ARM_MATH_ARMV8MML __DSP_PRESENT=1U + -fhonor-nans + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -9603,1694 +9640,10 @@ 0 0 0 - 0 + 1 - --cpreproc - ARM_MATH_ARMV8MML __CC_ARM - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x20000000 - - - - - - - - - - - - - Libraries - - - arm_math.lib - 4 - .\Lib\arm_math.lib - - - arm_ref.lib - 4 - .\Lib\arm_ref.lib - - - - - Startup - - - main.c - 1 - ..\..\Common\src\main.c - - - system_generic.c - 1 - ..\..\Common\platform\system_generic.c - - - startup_generic.S - 2 - ..\..\Common\platform\startup_generic.S - - - - - JTest - - - jtest_cycle.c - 1 - ..\..\Common\JTest\src\jtest_cycle.c - - - jtest_fw.c - 1 - ..\..\Common\JTest\src\jtest_fw.c - - - jtest_dump_str_segments.c - 1 - ..\..\Common\JTest\src\jtest_dump_str_segments.c - - - jtest_trigger_action.c - 1 - ..\..\Common\JTest\src\jtest_trigger_action.c - - - - - AllTests - - - all_tests.c - 1 - ..\..\Common\src\all_tests.c - - - - - Transform - - - cfft_tests.c - 1 - ..\..\Common\src\transform_tests\cfft_tests.c - - - transform_test_group.c - 1 - ..\..\Common\src\transform_tests\transform_test_group.c - - - transform_tests_common_data.c - 1 - ..\..\Common\src\transform_tests\transform_tests_common_data.c - - - cfft_family_tests.c - 1 - ..\..\Common\src\transform_tests\cfft_family_tests.c - - - rfft_tests.c - 1 - ..\..\Common\src\transform_tests\rfft_tests.c - - - rfft_fast_tests.c - 1 - ..\..\Common\src\transform_tests\rfft_fast_tests.c - - - dct4_tests.c - 1 - ..\..\Common\src\transform_tests\dct4_tests.c - - - - - BasicMath - - - basic_math_test_common_data.c - 1 - ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c - - - abs_tests.c - 1 - ..\..\Common\src\basic_math_tests\abs_tests.c - - - basic_math_test_group.c - 1 - ..\..\Common\src\basic_math_tests\basic_math_test_group.c - - - negate_tests.c - 1 - ..\..\Common\src\basic_math_tests\negate_tests.c - - - add_tests.c - 1 - ..\..\Common\src\basic_math_tests\add_tests.c - - - mult_tests.c - 1 - ..\..\Common\src\basic_math_tests\mult_tests.c - - - sub_tests.c - 1 - ..\..\Common\src\basic_math_tests\sub_tests.c - - - dot_prod_tests.c - 1 - ..\..\Common\src\basic_math_tests\dot_prod_tests.c - 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### uVision Project, (C) Keil Software
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..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + 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$$Device:ARMv8MML_DSP_SP$Device\ARM\SVD\ARMv8MML.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\ARMv8MMLldfsp\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\ARMv8MMLldfsp\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pV8MML + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4097 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "ARMV8MML" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + 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0x20000000 + + ..\..\Common\platform\ARMCLANG\armcc6_arm.sct + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + + + + + + + + diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt deleted file mode 100644 index 79e96c4..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt +++ /dev/null @@ -1,163 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt deleted file mode 100644 index 8ff1d62..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt deleted file mode 100644 index e6f8798..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt deleted file mode 100644 index 5c562f2..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt deleted file mode 100644 index de6a271..0000000 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt +++ /dev/null @@ -1,183 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#---------------------------------------------------------------------------------------------- -cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] -fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] -fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb -fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. -fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation -fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) -fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode -fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected -fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] -fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART -fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence -fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size -fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision -fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address -fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface -fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking -fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] -fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] -fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] -fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] -fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS -fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer -fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay -fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] -#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt new file mode 100644 index 0000000..d9cb90a --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt new file mode 100644 index 0000000..9c3cfc2 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt new file mode 100644 index 0000000..011260a --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt new file mode 100644 index 0000000..2a0a82a --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt new file mode 100644 index 0000000..4140d9b --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx index 48cafe1..79f27f0 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx @@ -101,7 +101,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -138,7 +140,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"..\cortexM0l_config.txt" -MA"-Q 1" 0 @@ -185,6 +187,10 @@ + + + + @@ -268,7 +274,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -285,7 +293,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"..\cortexM3l_config.txt" -MA"-Q 1" 0 @@ -332,6 +340,10 @@ + + + + @@ -415,7 +427,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -432,7 +446,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4l_config.txt" -MA"-Q 1" 0 @@ -479,6 +493,10 @@ + + + + @@ -562,7 +580,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -599,7 +619,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1" 0 @@ -646,6 +666,10 @@ + + + + @@ -729,7 +753,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -766,7 +792,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7l_config.txt" -MA"-Q 1" 0 @@ -813,6 +839,10 @@ + + + + @@ -896,7 +926,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -933,7 +965,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfsp_config.txt" -MA"-Q 1" 0 @@ -980,6 +1012,10 @@ + + + + @@ -1063,7 +1099,9 @@ 0 0 1 - 4 + 0 + 0 + 5 @@ -1080,7 +1118,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA + -I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfdp_config.txt" -MA"-Q 1" 0 @@ -1127,6 +1165,10 @@ + + + + @@ -1210,6 +1252,8 @@ 0 0 1 + 0 + 0 15 @@ -1242,7 +1286,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1" 0 @@ -1289,6 +1333,10 @@ + + + + @@ -1372,6 +1420,8 @@ 0 0 1 + 0 + 0 15 @@ -1389,7 +1439,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1" 0 @@ -1436,6 +1486,10 @@ + + + + @@ -1519,6 +1573,8 @@ 0 0 1 + 0 + 0 15 @@ -1551,7 +1607,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_FP_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1" 0 @@ -1598,141 +1654,10 @@ - - - - - ARMv8MMLlfdp.DoNotUse - 0x3 - ARM-GNU - - 12000000 - - 0 - 1 - 1 - 0 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 120 - 65 - 8 - .\IntermediateFiles\ARMv8MMLlfdp\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 0 - - 7 - - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - -1 - - - - - - - - - - - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - + + + + @@ -1816,6 +1741,8 @@ 0 0 1 + 0 + 0 15 @@ -1848,7 +1775,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1" 0 @@ -1895,6 +1822,10 @@ + + + + @@ -1978,6 +1909,8 @@ 0 0 1 + 0 + 0 15 @@ -2010,7 +1943,7 @@ 0 DbgFMv8M - -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_config.txt" -MA + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA"-Q 1" 0 @@ -2057,141 +1990,10 @@ - - - - - ARMv8MMLldfdp.DoNotUse - 0x3 - ARM-GNU - - 12000000 - - 0 - 1 - 1 - 0 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 120 - 65 - 8 - .\IntermediateFiles\ARMv8MMLldfdp\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 0 - - 7 - - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - -1 - - - - - - - - - - - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - + + + + diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx index 0b5c53b..7d12245 100644 --- a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx @@ -10,11 +10,12 @@ cortexM0l 0x3 ARM-GNU + 0 ARMCM0 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE @@ -131,7 +132,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -166,6 +167,7 @@ 0 0 0 + 0 0 0 @@ -238,9 +240,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections - ARM_MATH_CM0 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -248,7 +250,7 @@ 0 - ARM_MATH_CM0 + ARMCM0 @@ -734,11 +736,12 @@ cortexM3l 0x3 ARM-GNU + 0 ARMCM3 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -855,7 +858,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -890,6 +893,7 @@ 0 0 0 + 0 0 0 @@ -962,9 +966,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections - ARM_MATH_CM3 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -972,7 +976,7 @@ 0 - ARM_MATH_CM3 + ARMCM3 @@ -1458,11 +1462,12 @@ cortexM4l 0x3 ARM-GNU + 0 ARMCM4 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE @@ -1579,7 +1584,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -1614,6 +1619,7 @@ 0 0 0 + 0 0 0 @@ -1686,9 +1692,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections - ARM_MATH_CM4 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -1696,7 +1702,7 @@ 0 - ARM_MATH_CM4 + ARMCM4 @@ -2182,11 +2188,12 @@ cortexM4lf 0x3 ARM-GNU + 0 ARMCM4_FP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE @@ -2303,7 +2310,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -2338,6 +2345,7 @@ 0 0 2 + 0 0 0 @@ -2410,9 +2418,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffp-contract=off - ARM_MATH_CM4 __FPU_PRESENT=1U + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -2420,7 +2428,7 @@ 0 - ARM_MATH_CM4 + ARMCM4 @@ -2906,11 +2914,12 @@ cortexM7l 0x3 ARM-GNU + 0 ARMCM7 ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE @@ -3027,7 +3036,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -3062,6 +3071,7 @@ 0 0 0 + 0 0 0 @@ -3134,9 +3144,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections - ARM_MATH_CM7 + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -3144,7 +3154,7 @@ 0 - ARM_MATH_CM7 + ARMCM7 @@ -3630,11 +3640,12 @@ cortexM7lfsp 0x3 ARM-GNU + 0 ARMCM7_SP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE @@ -3751,7 +3762,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -3786,6 +3797,7 @@ 0 0 2 + 0 0 0 @@ -3858,9 +3870,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off - ARM_MATH_CM7 __FPU_PRESENT=1U + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -3868,7 +3880,7 @@ 0 - ARM_MATH_CM7 + ARMCM7 @@ -4354,11 +4366,12 @@ cortexM7lfdp 0x3 ARM-GNU + 0 ARMCM7_DP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE @@ -4475,7 +4488,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -4510,6 +4523,7 @@ 0 0 3 + 0 0 0 @@ -4582,9 +4596,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv5-d16 -mfloat-abi=hard -ffp-contract=off - ARM_MATH_CM7 __FPU_PRESENT=1U + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -4592,7 +4606,7 @@ 0 - ARM_MATH_CM7 + ARMCM7 @@ -5078,11 +5092,12 @@ ARMv8MBLl 0x3 ARM-GNU + 0 ARMv8MBL ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE @@ -5199,7 +5214,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -5234,6 +5249,7 @@ 0 0 2 + 0 1 1 @@ -5306,9 +5322,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.base - ARM_MATH_ARMV8MBL + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -5316,7 +5332,7 @@ 0 - ARM_MATH_ARMV8MBL + ARMv8MBL @@ -5802,11 +5818,12 @@ ARMv8MMLl 0x3 ARM-GNU + 0 ARMv8MML ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") TZ CLOCK(12000000) ESEL ELITTLE @@ -5923,7 +5940,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -5958,6 +5975,7 @@ 0 0 2 + 0 1 1 @@ -6030,9 +6048,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main - ARM_MATH_ARMV8MML + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -6040,7 +6058,7 @@ 0 - ARM_MATH_ARMV8MML + ARMv8MML @@ -6526,11 +6544,12 @@ ARMv8MMLlfsp 0x3 ARM-GNU + 0 ARMv8MML_SP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) TZ CLOCK(12000000) ESEL ELITTLE @@ -6647,7 +6666,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -6682,6 +6701,7 @@ 0 0 2 + 0 1 1 @@ -6754,9 +6774,9 @@ 1 -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off - ARM_MATH_ARMV8MML __FPU_PRESENT=1U + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -6764,7 +6784,7 @@ 0 - ARM_MATH_ARMV8MML + ARMv8MML @@ -7247,1469 +7267,22 @@ - ARMv8MMLlfdp.DoNotUse - 0x3 - ARM-GNU - - - ARMv8MML_DP - ARM - ARM.CMSIS.5.0.1-dev6 - http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(DFPU) TZ CLOCK(12000000) ESEL ELITTLE - - - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) - 0 - $$Device:ARMv8MML_DP$Device\ARM\ARMv8MML\Include\ARMv8MML_DP.h - - - - - - - - - - $$Device:ARMv8MML_DP$Device\ARM\SVD\ARMv8MML.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\IntermediateFiles\ARMv8MMLlfdp\ - DspLibTest_FVP - 1 - 0 - 0 - 1 - 1 - .\IntermediateFiles\ARMv8MMLlfdp\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - - - - SARMV8M.DLL - -MPU - TCM.DLL - -pV8MML - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2V8M.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "ARMV8MML" - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 3 - 1 - 1 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x200000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20200000 - 0x20000 - - - 1 - 0x200000 - 0x200000 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 1 - - -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=hard -ffp-contract=off - ARM_MATH_ARMV8MML __FPU_PRESENT=1U - - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests - - - - 0 - 0 - - - ARM_MATH_ARMV8MML - - - - - - 1 - 0 - 0 - 0 - 1 - - - - arm_math -larm_ref - .\Lib - -Wl,--gc-sections -march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=hard - ..\..\Common\platform\GCC\ARMCMx.ld - - - - - - Libraries - - - Startup - - - main.c - 1 - ..\..\Common\src\main.c - - - system_generic.c - 1 - ..\..\Common\platform\system_generic.c - - - startup_generic.S - 1 - ..\..\Common\platform\startup_generic.S - - - - - JTest - - - jtest_cycle.c - 1 - ..\..\Common\JTest\src\jtest_cycle.c - - - jtest_fw.c - 1 - ..\..\Common\JTest\src\jtest_fw.c - - - jtest_dump_str_segments.c - 1 - ..\..\Common\JTest\src\jtest_dump_str_segments.c - - - jtest_trigger_action.c - 1 - ..\..\Common\JTest\src\jtest_trigger_action.c - - - - - AllTests - - - all_tests.c - 1 - ..\..\Common\src\all_tests.c - - - - - Transform - - - cfft_tests.c - 1 - ..\..\Common\src\transform_tests\cfft_tests.c - - - transform_test_group.c - 1 - ..\..\Common\src\transform_tests\transform_test_group.c - - - transform_tests_common_data.c - 1 - ..\..\Common\src\transform_tests\transform_tests_common_data.c - - - cfft_family_tests.c - 1 - ..\..\Common\src\transform_tests\cfft_family_tests.c - - - rfft_tests.c - 1 - ..\..\Common\src\transform_tests\rfft_tests.c - - - rfft_fast_tests.c - 1 - ..\..\Common\src\transform_tests\rfft_fast_tests.c - - - dct4_tests.c - 1 - ..\..\Common\src\transform_tests\dct4_tests.c - - - - - BasicMath - - - basic_math_test_common_data.c - 1 - ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c - - - abs_tests.c - 1 - ..\..\Common\src\basic_math_tests\abs_tests.c - - - basic_math_test_group.c - 1 - ..\..\Common\src\basic_math_tests\basic_math_test_group.c - - - negate_tests.c - 1 - ..\..\Common\src\basic_math_tests\negate_tests.c - - - add_tests.c - 1 - ..\..\Common\src\basic_math_tests\add_tests.c - - - mult_tests.c - 1 - ..\..\Common\src\basic_math_tests\mult_tests.c - - - sub_tests.c - 1 - ..\..\Common\src\basic_math_tests\sub_tests.c - - - dot_prod_tests.c - 1 - ..\..\Common\src\basic_math_tests\dot_prod_tests.c - - - offset_tests.c - 1 - ..\..\Common\src\basic_math_tests\offset_tests.c - - - shift_tests.c - 1 - ..\..\Common\src\basic_math_tests\shift_tests.c - - - scale_tests.c - 1 - ..\..\Common\src\basic_math_tests\scale_tests.c - - - - - ComplexMath - - - complex_math_test_group.c - 1 - ..\..\Common\src\complex_math_tests\complex_math_test_group.c - - - complex_math_test_common_data.c - 1 - ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c - - - cmplx_conj_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c - - - cmplx_mag_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c - - - cmplx_mag_squared_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c - - - cmplx_dot_prod_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c - - - cmplx_mult_cmplx_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c - - - cmplx_mult_real_test.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c - - - - - Controller - - - controller_test_group.c - 1 - ..\..\Common\src\controller_tests\controller_test_group.c - - - pid_reset_tests.c - 1 - ..\..\Common\src\controller_tests\pid_reset_tests.c - - - sin_cos_tests.c - 1 - ..\..\Common\src\controller_tests\sin_cos_tests.c - - - pid_tests.c - 1 - ..\..\Common\src\controller_tests\pid_tests.c - - - controller_test_common_data.c - 1 - ..\..\Common\src\controller_tests\controller_test_common_data.c - - - - - FastMath - - - fast_math_tests.c - 1 - ..\..\Common\src\fast_math_tests\fast_math_tests.c - - - fast_math_tests_common_data.c - 1 - ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c - - - - - Filtering - - - filtering_test_common_data.c - 1 - ..\..\Common\src\filtering_tests\filtering_test_common_data.c - - - filtering_test_group.c - 1 - ..\..\Common\src\filtering_tests\filtering_test_group.c - - - biquad_tests.c - 1 - ..\..\Common\src\filtering_tests\biquad_tests.c - - - conv_tests.c - 1 - ..\..\Common\src\filtering_tests\conv_tests.c - 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- - mat_init_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_init_tests.c - - - mat_scale_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_scale_tests.c - - - - - Statistics - - - max_tests.c - 1 - ..\..\Common\src\statistics_tests\max_tests.c - - - statistics_test_common_data.c - 1 - ..\..\Common\src\statistics_tests\statistics_test_common_data.c - - - statistics_test_group.c - 1 - ..\..\Common\src\statistics_tests\statistics_test_group.c - - - mean_tests.c - 1 - ..\..\Common\src\statistics_tests\mean_tests.c - - - min_tests.c - 1 - ..\..\Common\src\statistics_tests\min_tests.c - - - power_tests.c - 1 - ..\..\Common\src\statistics_tests\power_tests.c - - - rms_tests.c - 1 - ..\..\Common\src\statistics_tests\rms_tests.c - - - std_tests.c - 1 - ..\..\Common\src\statistics_tests\std_tests.c - - - var_tests.c - 1 - ..\..\Common\src\statistics_tests\var_tests.c - - - - - Support - - - copy_tests.c - 1 - ..\..\Common\src\support_tests\copy_tests.c - - - support_test_common_data.c - 1 - ..\..\Common\src\support_tests\support_test_common_data.c - - - support_test_group.c - 1 - ..\..\Common\src\support_tests\support_test_group.c - - - fill_tests.c - 1 - ..\..\Common\src\support_tests\fill_tests.c - - - x_to_y_tests.c - 1 - ..\..\Common\src\support_tests\x_to_y_tests.c - - - - - Intrinsics - - - intrinsics_tests.c - 1 - ..\..\Common\src\intrinsics_tests\intrinsics_tests.c - - - intrinsics_tests_common_data.c - 1 - ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c - - - - - MathHelper - - - math_helper.c - 1 - ..\..\Common\src\math_helper.c - - - - - - - ARMv8MMLld - 0x3 - ARM-GNU - - - ARMv8MML_DSP - ARM - ARM.CMSIS.5.0.1-dev6 - http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") DSP TZ CLOCK(12000000) ESEL ELITTLE - - - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) - 0 - $$Device:ARMv8MML_DSP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP.h - - - - - - - - - - $$Device:ARMv8MML_DSP$Device\ARM\SVD\ARMv8MML.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\IntermediateFiles\ARMv8MMLld\ - DspLibTest_FVP - 1 - 0 - 0 - 1 - 1 - .\IntermediateFiles\ARMv8MMLld\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - - - - SARMV8M.DLL - -MPU - TCM.DLL - -pV8MML - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2V8M.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "ARMV8MML" - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 1 - 1 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x200000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20200000 - 0x20000 - - - 1 - 0x200000 - 0x200000 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 1 - - -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp - ARM_MATH_ARMV8MML __DSP_PRESENT=1U - - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests - - - - 0 - 0 - - - ARM_MATH_ARMV8MML - - - - - - 1 - 0 - 0 - 0 - 1 - - - - arm_math -larm_ref - .\Lib - -Wl,--gc-sections -march=armv8-m.main+dsp - ..\..\Common\platform\GCC\ARMCMx.ld - - - - - - Libraries - - - Startup - - - main.c - 1 - ..\..\Common\src\main.c - - - system_generic.c - 1 - ..\..\Common\platform\system_generic.c - - - startup_generic.S - 1 - ..\..\Common\platform\startup_generic.S - - - - - JTest - - - jtest_cycle.c - 1 - ..\..\Common\JTest\src\jtest_cycle.c - - - jtest_fw.c - 1 - ..\..\Common\JTest\src\jtest_fw.c - - - jtest_dump_str_segments.c - 1 - ..\..\Common\JTest\src\jtest_dump_str_segments.c - - - jtest_trigger_action.c - 1 - ..\..\Common\JTest\src\jtest_trigger_action.c - - - - - AllTests - - - all_tests.c - 1 - ..\..\Common\src\all_tests.c - - - - - Transform - - - cfft_tests.c - 1 - ..\..\Common\src\transform_tests\cfft_tests.c - - - transform_test_group.c - 1 - ..\..\Common\src\transform_tests\transform_test_group.c - - - transform_tests_common_data.c - 1 - ..\..\Common\src\transform_tests\transform_tests_common_data.c - - - cfft_family_tests.c - 1 - ..\..\Common\src\transform_tests\cfft_family_tests.c - - - rfft_tests.c - 1 - ..\..\Common\src\transform_tests\rfft_tests.c - - - rfft_fast_tests.c - 1 - ..\..\Common\src\transform_tests\rfft_fast_tests.c - - - dct4_tests.c - 1 - ..\..\Common\src\transform_tests\dct4_tests.c - - - - - BasicMath - - - basic_math_test_common_data.c - 1 - ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c - - - abs_tests.c - 1 - ..\..\Common\src\basic_math_tests\abs_tests.c - - - basic_math_test_group.c - 1 - ..\..\Common\src\basic_math_tests\basic_math_test_group.c - - - negate_tests.c - 1 - ..\..\Common\src\basic_math_tests\negate_tests.c - - - add_tests.c - 1 - ..\..\Common\src\basic_math_tests\add_tests.c - - - mult_tests.c - 1 - ..\..\Common\src\basic_math_tests\mult_tests.c - - - sub_tests.c - 1 - ..\..\Common\src\basic_math_tests\sub_tests.c - - - dot_prod_tests.c - 1 - ..\..\Common\src\basic_math_tests\dot_prod_tests.c - - - offset_tests.c - 1 - ..\..\Common\src\basic_math_tests\offset_tests.c - - - shift_tests.c - 1 - ..\..\Common\src\basic_math_tests\shift_tests.c - - - scale_tests.c - 1 - ..\..\Common\src\basic_math_tests\scale_tests.c - - - - - ComplexMath - - - complex_math_test_group.c - 1 - ..\..\Common\src\complex_math_tests\complex_math_test_group.c - - - complex_math_test_common_data.c - 1 - ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c - - - cmplx_conj_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c - - - cmplx_mag_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c - - - cmplx_mag_squared_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c - - - cmplx_dot_prod_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c - - - cmplx_mult_cmplx_tests.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c - - - cmplx_mult_real_test.c - 1 - ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c - - - - - Controller - - - controller_test_group.c - 1 - ..\..\Common\src\controller_tests\controller_test_group.c - - - pid_reset_tests.c - 1 - ..\..\Common\src\controller_tests\pid_reset_tests.c - - - sin_cos_tests.c - 1 - ..\..\Common\src\controller_tests\sin_cos_tests.c - - - pid_tests.c - 1 - ..\..\Common\src\controller_tests\pid_tests.c - - - controller_test_common_data.c - 1 - ..\..\Common\src\controller_tests\controller_test_common_data.c - - - - - FastMath - - - fast_math_tests.c - 1 - ..\..\Common\src\fast_math_tests\fast_math_tests.c - - - fast_math_tests_common_data.c - 1 - ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c - - - - - Filtering - - - filtering_test_common_data.c - 1 - ..\..\Common\src\filtering_tests\filtering_test_common_data.c - - - filtering_test_group.c - 1 - ..\..\Common\src\filtering_tests\filtering_test_group.c - - - biquad_tests.c - 1 - ..\..\Common\src\filtering_tests\biquad_tests.c - - - conv_tests.c - 1 - ..\..\Common\src\filtering_tests\conv_tests.c - - - correlate_tests.c - 1 - ..\..\Common\src\filtering_tests\correlate_tests.c - - - fir_tests.c - 1 - ..\..\Common\src\filtering_tests\fir_tests.c - - - iir_tests.c - 1 - ..\..\Common\src\filtering_tests\iir_tests.c - - - lms_tests.c - 1 - ..\..\Common\src\filtering_tests\lms_tests.c - - - - - Matrix - - - matrix_test_common_data.c - 1 - ..\..\Common\src\matrix_tests\matrix_test_common_data.c - - - matrix_test_group.c - 1 - ..\..\Common\src\matrix_tests\matrix_test_group.c - - - mat_cmplx_mult_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c - - - mat_add_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_add_tests.c - - - mat_mult_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_mult_tests.c - - - mat_mult_fast_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c - - - mat_sub_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_sub_tests.c - - - mat_inverse_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_inverse_tests.c - - - mat_trans_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_trans_tests.c - - - mat_init_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_init_tests.c - - - mat_scale_tests.c - 1 - ..\..\Common\src\matrix_tests\mat_scale_tests.c - - - - - Statistics - - - max_tests.c - 1 - ..\..\Common\src\statistics_tests\max_tests.c - - - statistics_test_common_data.c - 1 - ..\..\Common\src\statistics_tests\statistics_test_common_data.c - - - statistics_test_group.c - 1 - ..\..\Common\src\statistics_tests\statistics_test_group.c - - - mean_tests.c - 1 - ..\..\Common\src\statistics_tests\mean_tests.c - - - min_tests.c - 1 - ..\..\Common\src\statistics_tests\min_tests.c - - - power_tests.c - 1 - ..\..\Common\src\statistics_tests\power_tests.c - - - rms_tests.c - 1 - ..\..\Common\src\statistics_tests\rms_tests.c - - - std_tests.c - 1 - ..\..\Common\src\statistics_tests\std_tests.c - - - var_tests.c - 1 - ..\..\Common\src\statistics_tests\var_tests.c - - - - - Support - - - copy_tests.c - 1 - ..\..\Common\src\support_tests\copy_tests.c - - - support_test_common_data.c - 1 - ..\..\Common\src\support_tests\support_test_common_data.c - - - support_test_group.c - 1 - ..\..\Common\src\support_tests\support_test_group.c - - - fill_tests.c - 1 - ..\..\Common\src\support_tests\fill_tests.c - - - x_to_y_tests.c - 1 - ..\..\Common\src\support_tests\x_to_y_tests.c - - - - - Intrinsics - - - intrinsics_tests.c - 1 - ..\..\Common\src\intrinsics_tests\intrinsics_tests.c - - - intrinsics_tests_common_data.c - 1 - ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c - - - - - MathHelper - - - math_helper.c - 1 - ..\..\Common\src\math_helper.c - - - - - - - ARMv8MMLldfsp + ARMv8MMLld 0x3 ARM-GNU + 0 - ARMv8MML_DSP_SP + ARMv8MML_DSP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") DSP TZ CLOCK(12000000) ESEL ELITTLE UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) 0 - $$Device:ARMv8MML_DSP_SP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP_SP.h + $$Device:ARMv8MML_DSP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP.h @@ -8719,7 +7292,7 @@ - $$Device:ARMv8MML_DSP_SP$Device\ARM\SVD\ARMv8MML.svd + $$Device:ARMv8MML_DSP$Device\ARM\SVD\ARMv8MML.svd 0 0 @@ -8734,14 +7307,14 @@ 0 1 - .\IntermediateFiles\ARMv8MMLldfsp\ + .\IntermediateFiles\ARMv8MMLld\ DspLibTest_FVP 1 0 0 1 1 - .\IntermediateFiles\ARMv8MMLldfsp\ + .\IntermediateFiles\ARMv8MMLld\ 1 0 0 @@ -8819,7 +7392,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -8854,6 +7427,7 @@ 0 0 2 + 0 1 1 @@ -8925,10 +7499,10 @@ 2 1 - -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off - ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U + -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -8936,7 +7510,7 @@ 0 - ARM_MATH_ARMV8MML + ARMv8MML @@ -8952,7 +7526,7 @@ arm_math -larm_ref .\Lib - -Wl,--gc-sections -march=armv8-m.main+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard + -Wl,--gc-sections -march=armv8-m.main+dsp ..\..\Common\platform\GCC\ARMCMx.ld @@ -9419,21 +7993,22 @@ - ARMv8MMLldfdp.DoNotUse + ARMv8MMLldfsp 0x3 ARM-GNU + 0 - ARMv8MML_DSP_DP + ARMv8MML_DSP_SP ARM - ARM.CMSIS.5.0.1-dev6 + ARM.CMSIS.5.5.0-dev52 http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(DFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) 0 - $$Device:ARMv8MML_DSP_DP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP_DP.h + $$Device:ARMv8MML_DSP_SP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP_SP.h @@ -9443,7 +8018,7 @@ - $$Device:ARMv8MML_DSP_DP$Device\ARM\SVD\ARMv8MML.svd + $$Device:ARMv8MML_DSP_SP$Device\ARM\SVD\ARMv8MML.svd 0 0 @@ -9458,14 +8033,14 @@ 0 1 - .\IntermediateFiles\ARMv8MMLldfdp\ + .\IntermediateFiles\ARMv8MMLldfsp\ DspLibTest_FVP 1 0 0 1 1 - .\IntermediateFiles\ARMv8MMLldfdp\ + .\IntermediateFiles\ARMv8MMLldfsp\ 1 0 0 @@ -9543,7 +8118,7 @@ 0 0 1 - 1 + 0 4096 1 @@ -9577,7 +8152,8 @@ 1 0 0 - 3 + 2 + 0 1 1 @@ -9649,10 +8225,10 @@ 2 1 - -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp -mfpu=fpv5-d16 -mfloat-abi=hard -ffp-contract=off - ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U + -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off + - ..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + ..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests @@ -9660,7 +8236,7 @@ 0 - ARM_MATH_ARMV8MML + ARMv8MML @@ -9676,7 +8252,7 @@ arm_math -larm_ref .\Lib - -Wl,--gc-sections -march=armv8-m.main+dsp -mfpu=fpv5-d16 -mfloat-abi=hard + -Wl,--gc-sections -march=armv8-m.main+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard ..\..\Common\platform\GCC\ARMCMx.ld diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt new file mode 100644 index 0000000..8e33c76 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt new file mode 100644 index 0000000..2caf254 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm3ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm3ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt new file mode 100644 index 0000000..1c9fece --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt new file mode 100644 index 0000000..eb832ed --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt new file mode 100644 index 0000000..4e591c9 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- -- cgit