diff options
Diffstat (limited to 'tests/spi-master')
| -rw-r--r-- | tests/spi-master/Makefile | 15 | ||||
| -rw-r--r-- | tests/spi-master/Makefile.dut-stm32l073rz | 21 | ||||
| -rw-r--r-- | tests/spi-master/Makefile.host-stm32l1-generic | 18 | ||||
| -rw-r--r-- | tests/spi-master/README.md | 25 | ||||
| -rw-r--r-- | tests/spi-master/hw.h | 41 | ||||
| -rw-r--r-- | tests/spi-master/main-dut-stm32l073rz.c | 140 | ||||
| -rw-r--r-- | tests/spi-master/main-host-stm32l1-generic.c | 114 |
7 files changed, 0 insertions, 374 deletions
diff --git a/tests/spi-master/Makefile b/tests/spi-master/Makefile deleted file mode 100644 index 52841cd..0000000 --- a/tests/spi-master/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# This is just a stub makefile used for travis builds -# to keep things all compiling. Normally you'd use -# one of the makefiles directly. - -# These hoops are to enable parallel make correctly. -GZ_ALL := $(wildcard Makefile.*) - -all: $(GZ_ALL:=.all) -clean: $(GZ_ALL:=.clean) - -%.all: - make -f $* all -%.clean: - make -f $* clean - diff --git a/tests/spi-master/Makefile.dut-stm32l073rz b/tests/spi-master/Makefile.dut-stm32l073rz deleted file mode 100644 index 899c0fe..0000000 --- a/tests/spi-master/Makefile.dut-stm32l073rz +++ /dev/null @@ -1,21 +0,0 @@ -BOARD = dut-stm32l073rz -PROJECT = spi-master-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../../shared - -CFLAGS = -DSTDIO_USART=USART2 -CFILES = main-$(BOARD).c -#CFILES += spi-master.c -# No trace on cm0! -#CFILES += trace.c trace_stdio.c -CFILES += usart_stdio.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../../libopencm3 -DEVICE=stm32l073rz -OOCD_FILE = openocd.dut-stm32l073rz.cfg -include ../../rules.mk diff --git a/tests/spi-master/Makefile.host-stm32l1-generic b/tests/spi-master/Makefile.host-stm32l1-generic deleted file mode 100644 index 8996ff7..0000000 --- a/tests/spi-master/Makefile.host-stm32l1-generic +++ /dev/null @@ -1,18 +0,0 @@ -BOARD = host-stm32l1-generic -PROJECT = spi-slave-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../../shared - -CFILES = main-$(BOARD).c -#CFILES += spi-master.c -CFILES += trace.c trace_stdio.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../../libopencm3 -DEVICE=stm32l151xb -OOCD_FILE = openocd.stm32l1-generic.cfg -include ../../rules.mk diff --git a/tests/spi-master/README.md b/tests/spi-master/README.md deleted file mode 100644 index 504a074..0000000 --- a/tests/spi-master/README.md +++ /dev/null @@ -1,25 +0,0 @@ -SPI master mode tests - -While some of the disco boards have some form of spi device onboard, -which would, on the face of it, make testing easy, it's a different -device on each board, and there are boards without it. - -Instead, use a known SPI peripheral on all boards, and require/expect -a known fixed SPI slave device. Use a soft controller SPI slave device -for the far side, for double the test coverage! - -the "trigger" pin is bounced when each iteration of the test code starts, -allowing synchronization with a sigrok script that helps assure that -results are as expected. - -Debug is via SWO wherever possible, PA2 (tx only) on less capable cores - -Pinouts: - (red) (orange) (yellow)(brown) (black) -board CLK MISO MOSI CS periph trigger -f4-disco PB13 PB14 PB15 PB12 spi2 PB11 -l1-disco PB13 PB14 PB15 PB12 spi2 PB11 - - -Notes for monitoring with sigrok: -$ sigrok-cli -d fx2lafw -C D0=TRIG,D1=CS,D2=CLK,D3=MISO,D4=MOSI -c samplerate=12Mhz:captureratio=4 --time=150ms -t TRIG=r -P spi:clk=CLK:miso=MISO:mosi=MOSI -A spi=mosi-data diff --git a/tests/spi-master/hw.h b/tests/spi-master/hw.h deleted file mode 100644 index 2cbbea8..0000000 --- a/tests/spi-master/hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * March 2017 Karl Palsson <karlp@tweak.net.au> - */ - -#include <stdbool.h> -#include <stdint.h> - -#pragma once - -struct hw_detail -{ - uint32_t periph; /* eg: SPI2 */ - uint32_t periph_rcc; /* eg: RCC_SPI2 */ - uint32_t periph_rst; /* eg: RST_SPI2 */ - uint32_t pins; /* to set to the AF for the periph */ - uint32_t port; /* eg GPIOB */ - uint32_t port_rcc; /* for the gpio pins */ - uint32_t trigger_rcc; - uint32_t trigger_port; - uint32_t trigger_pin; -}; - -extern struct hw_detail hw_details; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Expected to setup clocks, turn on all peripherals, and configure - * any gpios necessary. - * @param hw pointer to hw details necessary - */ - void hw_setup(struct hw_detail* hw); - - /* let devices have a status led */ - void hw_set_led(bool val); - -#ifdef __cplusplus -} -#endif diff --git a/tests/spi-master/main-dut-stm32l073rz.c b/tests/spi-master/main-dut-stm32l073rz.c deleted file mode 100644 index 058d841..0000000 --- a/tests/spi-master/main-dut-stm32l073rz.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * March 2017 Karl Palsson <karlp@tweak.net.au> - */ - -#include <errno.h> -#include <stdio.h> -#include <unistd.h> -#include <libopencm3/cm3/nvic.h> -#include <libopencm3/stm32/gpio.h> -#include <libopencm3/stm32/rcc.h> -#include <libopencm3/stm32/spi.h> -#include <libopencm3/stm32/usart.h> - -#include "hw.h" - -#define LED_DISCO_GREEN_PORT GPIOB // actually cs -#define LED_DISCO_GREEN_PIN GPIO6 - - -struct hw_detail hw_details = { - .periph = SPI1, - .periph_rcc = RCC_SPI1, - .periph_rst = RST_SPI1, - .pins = GPIO5| GPIO6 | GPIO7, /* SPI pins for setting AF with */ - .port = GPIOA, - .port_rcc = RCC_GPIOA, - .trigger_rcc = RCC_GPIOB, - .trigger_port = GPIOB, - .trigger_pin = GPIO8, // pb6 is d7 on the LA -}; - - -/* provided in board files please*/ -/** - * Setup any gpios or anything hardware specific. - * Should _only_ be things that can't be done in shared init() - */ -static void hw_init(void) -{ - /* trigger pin gpio */ - rcc_periph_clock_enable(hw_details.trigger_rcc); - gpio_mode_setup(hw_details.trigger_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, hw_details.trigger_pin); - - /* spi control lines */ - rcc_periph_clock_enable(hw_details.port_rcc); - gpio_mode_setup(hw_details.port, GPIO_MODE_AF, GPIO_PUPD_NONE, hw_details.pins); - gpio_set_output_options(hw_details.port, GPIO_OTYPE_PP, GPIO_OSPEED_MED, hw_details.pins); - gpio_set_af(hw_details.port, GPIO_AF0, hw_details.pins); -} - -static void test_init(void) -{ - /* Setup SPI parameters. */ - rcc_periph_clock_enable(hw_details.periph_rcc); - spi_init_master(hw_details.periph, SPI_CR1_BAUDRATE_FPCLK_DIV_32, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); - /* Ignore the stupid NSS pin. */ - spi_enable_software_slave_management(hw_details.periph); - spi_set_nss_high(hw_details.periph); - - /* Finally enable the SPI. */ - spi_enable(hw_details.periph); -} - -static void test_task(void) { - static int i = 0; - printf("DUT iter %d\n", i++); - gpio_set(hw_details.trigger_port, hw_details.trigger_pin); - gpio_clear(LED_DISCO_GREEN_PORT, LED_DISCO_GREEN_PIN); - spi_xfer(hw_details.periph, 0xaa); - spi_xfer(hw_details.periph, 0x42); - spi_xfer(hw_details.periph, 0x69); - gpio_set(LED_DISCO_GREEN_PORT, LED_DISCO_GREEN_PIN); - gpio_clear(hw_details.trigger_port, hw_details.trigger_pin); -} - -static -void setup_usart(void) -{ - uint32_t dev = USART2; - rcc_periph_clock_enable(RCC_USART2); - rcc_periph_clock_enable(RCC_GPIOA); - gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2|GPIO3); - gpio_set_af(GPIOA, GPIO_AF4, GPIO2|GPIO3); - - usart_set_baudrate(dev, 115200); - usart_set_databits(dev, 8); - usart_set_parity(dev, USART_PARITY_NONE); - usart_set_stopbits(dev, USART_STOPBITS_1); - usart_set_mode(dev, USART_MODE_TX_RX); - usart_set_flow_control(dev, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(dev); -} - - -static void setup(void) -{ - setup_usart(); - printf("hi guys!\n"); - hw_init(); - test_init(); -} - - -int main(void) -{ - const struct rcc_clock_scale myclock = { - .pll_source = RCC_CFGR_PLLSRC_HSI16_CLK, - .pll_mul = RCC_CFGR_PLLMUL_MUL4, - .pll_div = RCC_CFGR_PLLDIV_DIV2, - .hpre = RCC_CFGR_HPRE_NODIV, - .ppre1 = RCC_CFGR_PPRE1_NODIV, - .ppre2 = RCC_CFGR_PPRE2_NODIV, - .voltage_scale = PWR_SCALE1, - .flash_waitstates = 1, - .ahb_frequency = 32e6, - .apb1_frequency = 32e6, - .apb2_frequency = 32e6, - }; - int i, j; - rcc_clock_setup_pll(&myclock); - rcc_periph_clock_enable(RCC_SYSCFG); - - /* green led for ticking */ - rcc_periph_clock_enable(RCC_GPIOB); - gpio_mode_setup(LED_DISCO_GREEN_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_DISCO_GREEN_PIN); - gpio_set(LED_DISCO_GREEN_PORT, LED_DISCO_GREEN_PIN); - setup(); - - while (1) { - test_task(); - //gpio_toggle(LED_DISCO_GREEN_PORT, LED_DISCO_GREEN_PIN); - for (i = 0; i < 0x80000; i++) { /* Wait a bit. */ - __asm__("NOP"); - } - } - return 0; -} diff --git a/tests/spi-master/main-host-stm32l1-generic.c b/tests/spi-master/main-host-stm32l1-generic.c deleted file mode 100644 index fa40ba1..0000000 --- a/tests/spi-master/main-host-stm32l1-generic.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * March 2017 Karl Palsson <karlp@tweak.net.au> - */ - -#include <errno.h> -#include <stdio.h> -#include <unistd.h> -#include <libopencm3/cm3/nvic.h> -#include <libopencm3/stm32/gpio.h> -#include <libopencm3/stm32/spi.h> -#include <libopencm3/stm32/rcc.h> - -#include "trace.h" - -#include "hw.h" - -struct hw_detail hw_details = { - .periph = SPI2, - .periph_rcc = RCC_SPI2, - .periph_rst = RST_SPI2, - .pins = GPIO13| GPIO14 | GPIO15, /* SPI pins for setting AF with */ - .port = GPIOB, - .port_rcc = RCC_GPIOB, - .trigger_rcc = RCC_GPIOB, - .trigger_port = GPIOB, - .trigger_pin = GPIO9, -}; - - -/* provided in board files please*/ -/** - * Setup any gpios or anything hardware specific. - * Should _only_ be things that can't be done in shared init() - */ -static void hw_init(void) -{ - /* trigger pin gpio */ - rcc_periph_clock_enable(hw_details.trigger_rcc); - gpio_mode_setup(hw_details.trigger_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, hw_details.trigger_pin); - - /* spi control lines */ - rcc_periph_clock_enable(hw_details.port_rcc); - gpio_mode_setup(hw_details.port, GPIO_MODE_AF, GPIO_PUPD_NONE, hw_details.pins); - gpio_set_output_options(hw_details.port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, hw_details.pins); - gpio_set_af(hw_details.port, GPIO_AF5, hw_details.pins); -} - -static void test_init(void) -{ - /* Setup SPI parameters. */ - rcc_periph_clock_enable(hw_details.periph_rcc); - /* mostly, this is just "write 0 to cr1" */ - spi_set_slave_mode(hw_details.periph); - spi_send_msb_first(hw_details.periph); - spi_set_dff_8bit(hw_details.periph); - spi_set_clock_phase_0(hw_details.periph); - spi_set_clock_polarity_0(hw_details.periph); - spi_set_frf_motorola(hw_details.periph); - - /* we're a spi slave, use a CS pin */ - spi_disable_software_slave_management(hw_details.periph); - SPI_CR2(hw_details.periph) &= ~SPI_CR2_SSOE; - - /* Finally enable the SPI. */ - spi_enable(hw_details.periph); -} - -static void test_task(void) { - static int i = 0; - uint32_t spi = hw_details.periph; - if (SPI_SR(spi) & SPI_SR_TXE) { - /* ready to load next data in */ - SPI_DR(spi) = i++; - } - - if (SPI_SR(spi) & SPI_SR_RXNE) { - uint8_t data = SPI_DR(spi); - trace_send8(2, data); - } -} - - -static void setup(void) -{ - printf("hi guys!\n"); - hw_init(); - test_init(); -} - - -int main(void) -{ - const struct rcc_clock_scale myclock = { - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .pll_mul = RCC_CFGR_PLLMUL_MUL4, - .pll_div = RCC_CFGR_PLLDIV_DIV2, - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, - .voltage_scale = PWR_SCALE1, - .flash_waitstates = 1, - .ahb_frequency = 32e6, - .apb1_frequency = 32e6, - .apb2_frequency = 32e6, - }; - int i, j; - rcc_clock_setup_pll(&myclock); - setup(); - - while (1) { - test_task(); - } - return 0; -} |