summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2020-11-26Add CRC32 implementationjaseg7-2/+127
2020-11-25Add openocd configjaseg1-0/+10
2020-11-24Add prototype rotor firmware skeletonjaseg21-1/+1622
2020-11-13Fix titlejaseg1-1/+1
2020-11-06techrepor: Update paper. I think this is as far as I'll go before the prototype.jaseg2-131/+155
2020-11-05techreport: WIPjaseg2-198/+261
2020-10-30Update mech bomjaseg1-0/+0
2020-10-30Add mech bom, export 3d partsjaseg12-0/+123360
2020-10-29Add makefile, update mech foojaseg7-20/+107
2020-10-27tech-report: update bibliographyjaseg1-3/+27
2020-10-27Update tech reportjaseg3-25/+414
2020-10-22update tech reportjaseg1-131/+126
2020-10-14Fix up freecad model and add gerber exportjaseg2-0/+0
2020-10-13Fix up ALL the edge connectorsjaseg35-7395/+80281
2020-10-13Export bearing mount gerbersjaseg10-174/+228
2020-10-13Export raspi holder vertical strut pcbjaseg5-106/+78720
2020-10-13Export stator top PCBjaseg5-112/+75022
2020-10-13Update footprint library tablesjaseg8-5/+21
2020-10-13finish stator base pcbjaseg5-1158/+6823
2020-10-13Rotor base pcb: add debug connectorjaseg4-9254/+9233
2020-10-13Push new edge connector board outline to rotor basejaseg4-36/+129
2020-10-13rotor base dbg connect WIPjaseg3-2/+327
2020-10-13Fix rotor_base NRST and testpoint situationjaseg4-7393/+8607
2020-10-09Add meshes to PCBsjaseg25-76464/+139442
2020-10-09Layout more board, add proto areas to rotor basejaseg28-106406/+119750
2020-10-08Merge remote-tracking branch 'wendelstein/master'jaseg67-499/+3501
2020-10-08Route rotor base PCBjaseg5-946/+27487
2020-10-08TCC scenario performance: WIPjaseg1-0/+0
2020-10-07Merge HW dev and orga reposjaseg68-29/+4734
2020-10-07Add missing docsjaseg7-0/+2918
2020-10-02base schematic done, PCB WIPjaseg4-3098/+8540
2020-10-02schematic WIPjaseg3-19/+2636
2020-10-01Add images, translate FC -> KiCADjaseg17-85/+83114
2020-09-30Initial FC mech -> KiCAD PCB edge exportjaseg11-36/+216
2020-09-30Initial commitjaseg47-0/+2819
2020-09-18Finish first rough draftjaseg2-7/+191
2020-09-18Add prior art and engineering constraintsjaseg1-7/+121
2020-09-17Add contributions sectionjaseg1-1/+15
2020-09-16Initial commitjaseg4-0/+268
generated by cgit (git 2.34.1) at 2024-11-05 03:04:23 +0000