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authorjaseg <git@jaseg.net>2020-10-02 17:33:32 +0200
committerjaseg <git@jaseg.net>2020-10-02 17:33:32 +0200
commit2926e887c4360317809bd2a7eb4ad42290cfefe3 (patch)
treed180d9778a68baaa95824322ac98e9d248bb6754
downloaddbg-connect-2926e887c4360317809bd2a7eb4ad42290cfefe3.tar.gz
dbg-connect-2926e887c4360317809bd2a7eb4ad42290cfefe3.tar.bz2
dbg-connect-2926e887c4360317809bd2a7eb4ad42290cfefe3.zip
Initial commit
Diffstat
-rw-r--r--.gitignore1
-rw-r--r--cable/dbg_connect_cable/dbg_connect_cable.kicad_pcb354
-rw-r--r--cable/dbg_connect_cable/dbg_connect_cable.kicad_prl68
-rw-r--r--cable/dbg_connect_cable/dbg_connect_cable.kicad_pro367
-rw-r--r--cable/dbg_connect_cable/dbg_connect_cable.kicad_sch580
-rw-r--r--cable/dbg_connect_cable/fp-info-cache8
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-B_Cu.gbr87
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-B_Mask.gbr51
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-B_Paste.gbr15
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-B_SilkS.gbr86
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-Edge_Cuts.gbr26
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Cu.gbr311
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Mask.gbr531
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Paste.gbr39
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-F_SilkS.gbr49
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-NPTH.drl17
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-PTH.drl35
-rw-r--r--cable/dbg_connect_cable/gerber/dbg_connect_cable-job.gbrjob127
-rw-r--r--cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pcb433
-rw-r--r--cable/dbg_connect_cable_90/dbg_connect_cable.kicad_prl68
-rw-r--r--cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pro367
-rw-r--r--cable/dbg_connect_cable_90/dbg_connect_cable.kicad_sch580
-rw-r--r--cable/dbg_connect_cable_90/fp-info-cache8
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-B_Cu.gbr196
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-B_Mask.gbr51
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-B_Paste.gbr15
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-B_SilkS.gbr86
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-Edge_Cuts.gbr26
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Cu.gbr414
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Mask.gbr531
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Paste.gbr39
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_SilkS.gbr49
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-NPTH.drl17
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-PTH.drl42
-rw-r--r--cable/dbg_connect_cable_90/gerber/dbg_connect_cable-job.gbrjob127
-rw-r--r--common/common_footprints.pretty/EPT_EC.8_20pin.kicad_mod55
36 files changed, 5856 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..0a0d121
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*-backups
diff --git a/cable/dbg_connect_cable/dbg_connect_cable.kicad_pcb b/cable/dbg_connect_cable/dbg_connect_cable.kicad_pcb
new file mode 100644
index 0000000..94d289f
--- /dev/null
+++ b/cable/dbg_connect_cable/dbg_connect_cable.kicad_pcb
@@ -0,0 +1,354 @@
+(kicad_pcb (version 20200811) (host pcbnew "(5.99.0-2820-g96f4e8f6f)")
+
+ (general
+ (thickness 1.6)
+ (drawings 1)
+ (tracks 67)
+ (modules 3)
+ (nets 21)
+ )
+
+ (paper "A4")
+ (layers
+ (0 "F.Cu" signal)
+ (31 "B.Cu" signal)
+ (32 "B.Adhes" user)
+ (33 "F.Adhes" user)
+ (34 "B.Paste" user)
+ (35 "F.Paste" user)
+ (36 "B.SilkS" user)
+ (37 "F.SilkS" user)
+ (38 "B.Mask" user)
+ (39 "F.Mask" user)
+ (40 "Dwgs.User" user)
+ (41 "Cmts.User" user)
+ (42 "Eco1.User" user)
+ (43 "Eco2.User" user)
+ (44 "Edge.Cuts" user)
+ (45 "Margin" user)
+ (46 "B.CrtYd" user)
+ (47 "F.CrtYd" user)
+ (48 "B.Fab" user)
+ (49 "F.Fab" user)
+ )
+
+ (setup
+ (stackup
+ (layer "F.SilkS" (type "Top Silk Screen"))
+ (layer "F.Paste" (type "Top Solder Paste"))
+ (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
+ (layer "F.Cu" (type "copper") (thickness 0.035))
+ (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+ (layer "B.Cu" (type "copper") (thickness 0.035))
+ (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
+ (layer "B.Paste" (type "Bottom Solder Paste"))
+ (layer "B.SilkS" (type "Bottom Silk Screen"))
+ (copper_finish "None")
+ (dielectric_constraints no)
+ )
+ (pcbplotparams
+ (layerselection 0x010fc_ffffffff)
+ (usegerberextensions false)
+ (usegerberattributes true)
+ (usegerberadvancedattributes true)
+ (creategerberjobfile true)
+ (svguseinch false)
+ (svgprecision 6)
+ (excludeedgelayer true)
+ (linewidth 0.100000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15.000000)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (sketchpadsonfab false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory "gerber")
+ )
+ )
+
+ (net 0 "")
+ (net 1 "/B10")
+ (net 2 "/B9")
+ (net 3 "/B8")
+ (net 4 "/B7")
+ (net 5 "/B6")
+ (net 6 "/B5")
+ (net 7 "/B4")
+ (net 8 "/B3")
+ (net 9 "/B2")
+ (net 10 "/B1")
+ (net 11 "/A10")
+ (net 12 "/A9")
+ (net 13 "/A8")
+ (net 14 "/A7")
+ (net 15 "/A6")
+ (net 16 "/A5")
+ (net 17 "/A4")
+ (net 18 "/A3")
+ (net 19 "/A2")
+ (net 20 "/A1")
+
+ (module "common_footprints:EPT_EC.8_20pin" (layer "F.Cu") (tedit 5F774092) (tstamp c207d776-726d-480b-9558-c1adf17e6ef5)
+ (at 142 89 90)
+ (property "Reichelt" "EC.8 20")
+ (path "/3d1df27a-a102-4385-8696-8f0614142475")
+ (fp_text reference "J3" (at -6.3 -4.4 90 unlocked) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)) (justify left))
+ (tstamp 70aa0775-014b-47ac-8258-a8df007fe55c)
+ )
+ (fp_text value "EPT EC.8 20pin" (at 0 4.6 90 unlocked) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp f5037e59-d813-4658-9ca9-c6def9709a30)
+ )
+ (fp_rect (start -6.3 -3.5) (end 6.3 3.5) (layer "F.SilkS") (width 0.2) (tstamp de881cc2-b912-4e6d-900c-5df5f7cbeb29))
+ (pad "" np_thru_hole circle (at 5.2 0 90) (size 1.27 1.27) (drill 1.27) (layers *.Cu *.Mask)
+ (solder_mask_margin 0.01) (clearance 0.05) (tstamp 55eba3bb-671b-4cc5-a741-86b223940f2e))
+ (pad "" np_thru_hole circle (at -5.1 1.5 90) (size 1.27 1.27) (drill 1.27) (layers *.Cu *.Mask)
+ (solder_mask_margin 0.01) (clearance 0.05) (tstamp bd267e36-48fd-426a-bd26-acc17af20de2))
+ (pad "1" smd rect (at -3.6 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 20 "/A1") (pinfunction "Pin_1") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 5e2a3ac4-b7ae-4de6-be5f-c6047bc3e66b))
+ (pad "2" smd rect (at -3.6 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 10 "/B1") (pinfunction "Pin_2") (solder_mask_margin 0.01) (clearance 0.05) (tstamp e7721210-fa4c-4acb-ae98-8378651cf5c7))
+ (pad "3" smd rect (at -2.8 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 19 "/A2") (pinfunction "Pin_3") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 9dafcdc0-cd27-4659-aab7-921f3b8e14cf))
+ (pad "4" smd rect (at -2.8 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 9 "/B2") (pinfunction "Pin_4") (solder_mask_margin 0.01) (clearance 0.05) (tstamp e80e7a3e-da77-4ce2-ae89-4007dc299c65))
+ (pad "5" smd rect (at -2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 18 "/A3") (pinfunction "Pin_5") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 643014d6-72c2-4f4d-a7c4-bfc7b0b83a06))
+ (pad "6" smd rect (at -2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 8 "/B3") (pinfunction "Pin_6") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 9ae0ba6e-89e4-45e3-8d81-b22a12a3b98d))
+ (pad "7" smd rect (at -1.2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 17 "/A4") (pinfunction "Pin_7") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 3f89cc0f-95ff-4164-822c-1608e975b7e1))
+ (pad "8" smd rect (at -1.2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 7 "/B4") (pinfunction "Pin_8") (solder_mask_margin 0.01) (clearance 0.05) (tstamp ccbde77b-e584-4afa-81f5-deef96c684c8))
+ (pad "9" smd rect (at -0.4 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 16 "/A5") (pinfunction "Pin_9") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 1ffda658-7d6a-434a-88d8-4636bb182c95))
+ (pad "10" smd rect (at -0.4 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 6 "/B5") (pinfunction "Pin_10") (solder_mask_margin 0.01) (clearance 0.05) (tstamp bc35860c-6e2a-402b-a9ae-481432b3e0f6))
+ (pad "11" smd rect (at 0.4 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 15 "/A6") (pinfunction "Pin_11") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 229256d0-aaec-4bb7-b05b-6bc996e5f5bd))
+ (pad "12" smd rect (at 0.4 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 5 "/B6") (pinfunction "Pin_12") (solder_mask_margin 0.01) (clearance 0.05) (tstamp d52acd35-e3bb-4ba5-8c9a-70511c95272e))
+ (pad "13" smd rect (at 1.2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 14 "/A7") (pinfunction "Pin_13") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 53c1cdf6-043a-4bcc-90e1-ad1b6267aeae))
+ (pad "14" smd rect (at 1.2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 4 "/B7") (pinfunction "Pin_14") (solder_mask_margin 0.01) (clearance 0.05) (tstamp eab0e656-0e59-437b-a17b-c4fd04ab0b26))
+ (pad "15" smd rect (at 2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 13 "/A8") (pinfunction "Pin_15") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 2f020e3b-e6fd-498c-aa29-084f0595ec81))
+ (pad "16" smd rect (at 2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 3 "/B8") (pinfunction "Pin_16") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 670b9f32-541d-4906-aabb-c9d6f19dac23))
+ (pad "17" smd rect (at 2.8 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 12 "/A9") (pinfunction "Pin_17") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 3848c83f-f022-406e-a190-eea643349fec))
+ (pad "18" smd rect (at 2.8 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 2 "/B9") (pinfunction "Pin_18") (solder_mask_margin 0.01) (clearance 0.05) (tstamp f9d07626-193e-4d25-80e0-95889d31c3f8))
+ (pad "19" smd rect (at 3.6 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 11 "/A10") (pinfunction "Pin_19") (solder_mask_margin 0.01) (clearance 0.05) (tstamp efadc025-5295-4117-894e-76fc9c77d1a6))
+ (pad "20" smd rect (at 3.6 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 1 "/B10") (pinfunction "Pin_20") (solder_mask_margin 0.01) (clearance 0.05) (tstamp d103f9d8-ebca-4ad3-a67a-b9d13f8021f6))
+ )
+
+ (module "Connector_PinHeader_2.54mm:PinHeader_2x05_P2.54mm_Vertical" (layer "B.Cu") (tedit 59FED5CC) (tstamp 7e3389eb-1827-4dad-93d7-147fc82f0a9b)
+ (at 149 94)
+ (descr "Through hole straight pin header, 2x05, 2.54mm pitch, double rows")
+ (tags "Through hole pin header THT 2x05 2.54mm double row")
+ (path "/6b3463ed-6f77-4939-96a8-996fa4157a95")
+ (fp_text reference "J2" (at 1.27 2.33) (layer "B.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp ec7abf32-aeb5-4bb7-ba45-2bf4df3d5938)
+ )
+ (fp_text value "Conn_02x05_Odd_Even" (at 1.27 -12.49) (layer "B.Fab") hide
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp 0fa26bb7-54fc-4326-96a1-cf513f39ed83)
+ )
+ (fp_text user "${REFERENCE}" (at 1.27 -5.08 -90) (layer "B.Fab")
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp 6fef10bb-ed44-4c58-b790-3ee1782b4cc6)
+ )
+ (fp_line (start -1.33 -1.27) (end -1.33 -11.49) (layer "B.SilkS") (width 0.12) (tstamp 1074bce0-d550-4b7f-895d-fd14c8297e5f))
+ (fp_line (start -1.33 1.33) (end 0 1.33) (layer "B.SilkS") (width 0.12) (tstamp 53bfbb07-6ac0-4402-8765-22cdd9ea8724))
+ (fp_line (start 1.27 -1.27) (end 1.27 1.33) (layer "B.SilkS") (width 0.12) (tstamp 9f43c302-6094-4689-922a-536ea065a227))
+ (fp_line (start 3.87 1.33) (end 3.87 -11.49) (layer "B.SilkS") (width 0.12) (tstamp c8479459-98ab-4863-bdac-6965093e0511))
+ (fp_line (start 1.27 1.33) (end 3.87 1.33) (layer "B.SilkS") (width 0.12) (tstamp c91baab0-086e-40ee-b184-fc10b8d61b72))
+ (fp_line (start -1.33 0) (end -1.33 1.33) (layer "B.SilkS") (width 0.12) (tstamp cd9311e1-305f-4515-b637-afcf3e89f7ee))
+ (fp_line (start -1.33 -11.49) (end 3.87 -11.49) (layer "B.SilkS") (width 0.12) (tstamp f0d2c314-3757-416a-bd10-0b674401889f))
+ (fp_line (start -1.33 -1.27) (end 1.27 -1.27) (layer "B.SilkS") (width 0.12) (tstamp fbcc76a1-ea92-420f-a313-aedebfdb3f34))
+ (fp_line (start 4.35 1.8) (end -1.8 1.8) (layer "B.CrtYd") (width 0.05) (tstamp 27942762-87f2-4803-a079-90015015015d))
+ (fp_line (start -1.8 -11.95) (end 4.35 -11.95) (layer "B.CrtYd") (width 0.05) (tstamp 611dc478-0aac-401e-bee3-5bb328003a85))
+ (fp_line (start 4.35 -11.95) (end 4.35 1.8) (layer "B.CrtYd") (width 0.05) (tstamp bee4732d-41ac-4fdf-becc-236997510da5))
+ (fp_line (start -1.8 1.8) (end -1.8 -11.95) (layer "B.CrtYd") (width 0.05) (tstamp c97b7a40-226f-48c0-90bc-4849c5b26399))
+ (fp_line (start 3.81 1.27) (end 3.81 -11.43) (layer "B.Fab") (width 0.1) (tstamp 021a4e1f-5cb1-43e0-8801-51aa96c7be40))
+ (fp_line (start 0 1.27) (end 3.81 1.27) (layer "B.Fab") (width 0.1) (tstamp 5871cf0a-f48b-4194-8a2f-2721d132c2d0))
+ (fp_line (start -1.27 0) (end 0 1.27) (layer "B.Fab") (width 0.1) (tstamp 7bd76e79-f68a-4d76-b181-2d972eba1d85))
+ (fp_line (start 3.81 -11.43) (end -1.27 -11.43) (layer "B.Fab") (width 0.1) (tstamp 8d0e0701-73a6-46c3-9816-a55cbd07843a))
+ (fp_line (start -1.27 -11.43) (end -1.27 0) (layer "B.Fab") (width 0.1) (tstamp be61eaa2-bd6d-48d5-8028-e1197e5309f3))
+ (pad "1" thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (remove_unused_layers) (keep_end_layers)
+ (net 20 "/A1") (pinfunction "Pin_1") (tstamp 45b42be2-cea1-47b2-8879-272ff0e7abf4))
+ (pad "2" thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (remove_unused_layers) (keep_end_layers)
+ (net 19 "/A2") (pinfunction "Pin_2") (tstamp e0fb7058-f546-4279-9ec6-99b74ea8c3fa))
+ (pad "3" thru_hole oval (at 0 -2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (remove_unused_layers) (keep_end_layers)
+ (net 18 "/A3") (pinfunction "Pin_3") (tstamp 4beb6792-07bf-472b-ad1d-8017cf9b498c))
+ (pad "4" thru_hole oval (at 2.54 -2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 17 "/A4") (pinfunction "Pin_4") (tstamp 7a58c48b-1306-417e-9b55-8350ecd70605))
+ (pad "5" thru_hole oval (at 0 -5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 16 "/A5") (pinfunction "Pin_5") (tstamp beb08ce1-9ce1-4ee8-b81b-30c89cba792e))
+ (pad "6" thru_hole oval (at 2.54 -5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 15 "/A6") (pinfunction "Pin_6") (tstamp 9c632be4-bd26-47f8-b8db-1fdb3a5193e3))
+ (pad "7" thru_hole oval (at 0 -7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 14 "/A7") (pinfunction "Pin_7") (tstamp dfe0ca30-6633-4e05-976f-7cb2462cf2ad))
+ (pad "8" thru_hole oval (at 2.54 -7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 13 "/A8") (pinfunction "Pin_8") (tstamp 0e81ecb6-8a2d-49ac-9629-61448914cf4c))
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diff --git a/cable/dbg_connect_cable/dbg_connect_cable.kicad_prl b/cable/dbg_connect_cable/dbg_connect_cable.kicad_prl
new file mode 100644
index 0000000..e39594a
--- /dev/null
+++ b/cable/dbg_connect_cable/dbg_connect_cable.kicad_prl
@@ -0,0 +1,68 @@
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+ }
+}
diff --git a/cable/dbg_connect_cable/dbg_connect_cable.kicad_pro b/cable/dbg_connect_cable/dbg_connect_cable.kicad_pro
new file mode 100644
index 0000000..8fa011d
--- /dev/null
+++ b/cable/dbg_connect_cable/dbg_connect_cable.kicad_pro
@@ -0,0 +1,367 @@
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+ },
+ "legacy_lib_dir": "",
+ "legacy_lib_list": [],
+ "meta": {
+ "version": 0
+ },
+ "net_format_name": "",
+ "page_layout_descr_file": "",
+ "plot_directory": "",
+ "spice_adjust_passive_values": false,
+ "spice_external_command": "spice \"%I\"",
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+ },
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+ ],
+ "text_variables": {}
+}
diff --git a/cable/dbg_connect_cable/dbg_connect_cable.kicad_sch b/cable/dbg_connect_cable/dbg_connect_cable.kicad_sch
new file mode 100644
index 0000000..ed514e2
--- /dev/null
+++ b/cable/dbg_connect_cable/dbg_connect_cable.kicad_sch
@@ -0,0 +1,580 @@
+(kicad_sch (version 20200714) (host eeschema "(5.99.0-2820-g96f4e8f6f)")
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+ (page 1 1)
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-Edge_Cuts.gbr b/cable/dbg_connect_cable/gerber/dbg_connect_cable-Edge_Cuts.gbr
new file mode 100644
index 0000000..46b2c8f
--- /dev/null
+++ b/cable/dbg_connect_cable/gerber/dbg_connect_cable-Edge_Cuts.gbr
@@ -0,0 +1,26 @@
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Cu.gbr b/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Cu.gbr
new file mode 100644
index 0000000..7e2874c
--- /dev/null
+++ b/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Cu.gbr
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Mask.gbr b/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Mask.gbr
new file mode 100644
index 0000000..4655433
--- /dev/null
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Paste.gbr b/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Paste.gbr
new file mode 100644
index 0000000..f4f6832
--- /dev/null
+++ b/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_Paste.gbr
@@ -0,0 +1,39 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,(5.99.0-2820-g96f4e8f6f)*%
+%TF.CreationDate,2020-10-02T17:32:45+02:00*%
+%TF.ProjectId,dbg_connect_cable,6462675f-636f-46e6-9e65-63745f636162,rev?*%
+%TF.SameCoordinates,Original*%
+%TF.FileFunction,Paste,Top*%
+%TF.FilePolarity,Positive*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (5.99.0-2820-g96f4e8f6f)) date 2020-10-02 17:32:45*
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_SilkS.gbr b/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_SilkS.gbr
new file mode 100644
index 0000000..d8967f6
--- /dev/null
+++ b/cable/dbg_connect_cable/gerber/dbg_connect_cable-F_SilkS.gbr
@@ -0,0 +1,49 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,(5.99.0-2820-g96f4e8f6f)*%
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+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (5.99.0-2820-g96f4e8f6f)) date 2020-10-02 17:32:45*
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-NPTH.drl b/cable/dbg_connect_cable/gerber/dbg_connect_cable-NPTH.drl
new file mode 100644
index 0000000..ecaef72
--- /dev/null
+++ b/cable/dbg_connect_cable/gerber/dbg_connect_cable-NPTH.drl
@@ -0,0 +1,17 @@
+M48
+; DRILL file {KiCad (5.99.0-2820-g96f4e8f6f)} date Fri Oct 2 17:32:49 2020
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2020-10-02T17:32:49+02:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.99.0-2820-g96f4e8f6f)
+; #@! TF.FileFunction,NonPlated,1,2,NPTH
+FMAT,2
+INCH
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+%
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-PTH.drl b/cable/dbg_connect_cable/gerber/dbg_connect_cable-PTH.drl
new file mode 100644
index 0000000..9d1c180
--- /dev/null
+++ b/cable/dbg_connect_cable/gerber/dbg_connect_cable-PTH.drl
@@ -0,0 +1,35 @@
+M48
+; DRILL file {KiCad (5.99.0-2820-g96f4e8f6f)} date Fri Oct 2 17:32:49 2020
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2020-10-02T17:32:49+02:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.99.0-2820-g96f4e8f6f)
+; #@! TF.FileFunction,Plated,1,2,PTH
+FMAT,2
+INCH
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diff --git a/cable/dbg_connect_cable/gerber/dbg_connect_cable-job.gbrjob b/cable/dbg_connect_cable/gerber/dbg_connect_cable-job.gbrjob
new file mode 100644
index 0000000..25eea77
--- /dev/null
+++ b/cable/dbg_connect_cable/gerber/dbg_connect_cable-job.gbrjob
@@ -0,0 +1,127 @@
+{
+ "Header": {
+ "GenerationSoftware": {
+ "Vendor": "KiCad",
+ "Application": "Pcbnew",
+ "Version": "(5.99.0-2820-g96f4e8f6f)"
+ },
+ "CreationDate": "2020-10-02T17:32:47+02:00"
+ },
+ "GeneralSpecs": {
+ "ProjectId": {
+ "Name": "dbg_connect_cable",
+ "GUID": "6462675f-636f-46e6-9e65-63745f636162",
+ "Revision": "rev?"
+ },
+ "Size": {
+ "X": 25.6,
+ "Y": 17.1
+ },
+ "LayerNumber": 2,
+ "BoardThickness": 1.6,
+ "Finish": "None"
+ },
+ "DesignRules": [
+ {
+ "Layers": "Outer",
+ "PadToPad": 0.05,
+ "PadToTrack": 0.05,
+ "TrackToTrack": 0.2,
+ "MinLineWidth": 0.4
+ }
+ ],
+ "FilesAttributes": [
+ {
+ "Path": "dbg_connect_cable-F_Cu.gbr",
+ "FileFunction": "Copper,L1,Top",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-B_Cu.gbr",
+ "FileFunction": "Copper,L2,Bot",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-F_Paste.gbr",
+ "FileFunction": "SolderPaste,Top",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-B_Paste.gbr",
+ "FileFunction": "SolderPaste,Bot",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-F_SilkS.gbr",
+ "FileFunction": "Legend,Top",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-B_SilkS.gbr",
+ "FileFunction": "Legend,Bot",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-F_Mask.gbr",
+ "FileFunction": "SolderMask,Top",
+ "FilePolarity": "Negative"
+ },
+ {
+ "Path": "dbg_connect_cable-B_Mask.gbr",
+ "FileFunction": "SolderMask,Bot",
+ "FilePolarity": "Negative"
+ },
+ {
+ "Path": "dbg_connect_cable-Edge_Cuts.gbr",
+ "FileFunction": "Profile",
+ "FilePolarity": "Positive"
+ }
+ ],
+ "MaterialStackup": [
+ {
+ "Type": "Legend",
+ "Name": "Top Silk Screen"
+ },
+ {
+ "Type": "SolderPaste",
+ "Name": "Top Solder Paste"
+ },
+ {
+ "Type": "SolderMask",
+ "Color": "Green",
+ "Thickness": 0.01,
+ "Name": "Top Solder Mask"
+ },
+ {
+ "Type": "Copper",
+ "Thickness": 0.035,
+ "Name": "F.Cu"
+ },
+ {
+ "Type": "Dielectric",
+ "Thickness": 1.51,
+ "Material": "FR4",
+ "Name": "F.Cu/B.Cu",
+ "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
+ },
+ {
+ "Type": "Copper",
+ "Thickness": 0.035,
+ "Name": "B.Cu"
+ },
+ {
+ "Type": "SolderMask",
+ "Color": "Green",
+ "Thickness": 0.01,
+ "Name": "Bottom Solder Mask"
+ },
+ {
+ "Type": "SolderPaste",
+ "Name": "Bottom Solder Paste"
+ },
+ {
+ "Type": "Legend",
+ "Name": "Bottom Silk Screen"
+ }
+ ]
+}
diff --git a/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pcb b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pcb
new file mode 100644
index 0000000..7bcd0d4
--- /dev/null
+++ b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pcb
@@ -0,0 +1,433 @@
+(kicad_pcb (version 20200811) (host pcbnew "(5.99.0-2820-g96f4e8f6f)")
+
+ (general
+ (thickness 1.6)
+ (drawings 1)
+ (tracks 146)
+ (modules 3)
+ (nets 21)
+ )
+
+ (paper "A4")
+ (layers
+ (0 "F.Cu" signal)
+ (31 "B.Cu" signal)
+ (32 "B.Adhes" user)
+ (33 "F.Adhes" user)
+ (34 "B.Paste" user)
+ (35 "F.Paste" user)
+ (36 "B.SilkS" user)
+ (37 "F.SilkS" user)
+ (38 "B.Mask" user)
+ (39 "F.Mask" user)
+ (40 "Dwgs.User" user)
+ (41 "Cmts.User" user)
+ (42 "Eco1.User" user)
+ (43 "Eco2.User" user)
+ (44 "Edge.Cuts" user)
+ (45 "Margin" user)
+ (46 "B.CrtYd" user)
+ (47 "F.CrtYd" user)
+ (48 "B.Fab" user)
+ (49 "F.Fab" user)
+ )
+
+ (setup
+ (stackup
+ (layer "F.SilkS" (type "Top Silk Screen"))
+ (layer "F.Paste" (type "Top Solder Paste"))
+ (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
+ (layer "F.Cu" (type "copper") (thickness 0.035))
+ (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+ (layer "B.Cu" (type "copper") (thickness 0.035))
+ (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
+ (layer "B.Paste" (type "Bottom Solder Paste"))
+ (layer "B.SilkS" (type "Bottom Silk Screen"))
+ (copper_finish "None")
+ (dielectric_constraints no)
+ )
+ (pcbplotparams
+ (layerselection 0x010fc_ffffffff)
+ (usegerberextensions false)
+ (usegerberattributes true)
+ (usegerberadvancedattributes true)
+ (creategerberjobfile true)
+ (svguseinch false)
+ (svgprecision 6)
+ (excludeedgelayer true)
+ (linewidth 0.100000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15.000000)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (sketchpadsonfab false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory "gerber")
+ )
+ )
+
+ (net 0 "")
+ (net 1 "/B10")
+ (net 2 "/B9")
+ (net 3 "/B8")
+ (net 4 "/B7")
+ (net 5 "/B6")
+ (net 6 "/B5")
+ (net 7 "/B4")
+ (net 8 "/B3")
+ (net 9 "/B2")
+ (net 10 "/B1")
+ (net 11 "/A10")
+ (net 12 "/A9")
+ (net 13 "/A8")
+ (net 14 "/A7")
+ (net 15 "/A6")
+ (net 16 "/A5")
+ (net 17 "/A4")
+ (net 18 "/A3")
+ (net 19 "/A2")
+ (net 20 "/A1")
+
+ (module "common_footprints:EPT_EC.8_20pin" (layer "F.Cu") (tedit 5F774092) (tstamp c207d776-726d-480b-9558-c1adf17e6ef5)
+ (at 142 89 90)
+ (property "Reichelt" "EC.8 20")
+ (path "/3d1df27a-a102-4385-8696-8f0614142475")
+ (fp_text reference "J3" (at -6.3 -4.4 90 unlocked) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)) (justify left))
+ (tstamp 70aa0775-014b-47ac-8258-a8df007fe55c)
+ )
+ (fp_text value "EPT EC.8 20pin" (at 0 4.6 90 unlocked) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp f5037e59-d813-4658-9ca9-c6def9709a30)
+ )
+ (fp_rect (start -6.3 -3.5) (end 6.3 3.5) (layer "F.SilkS") (width 0.2) (tstamp de881cc2-b912-4e6d-900c-5df5f7cbeb29))
+ (pad "" np_thru_hole circle (at 5.2 0 90) (size 1.27 1.27) (drill 1.27) (layers *.Cu *.Mask)
+ (solder_mask_margin 0.01) (clearance 0.05) (tstamp 55eba3bb-671b-4cc5-a741-86b223940f2e))
+ (pad "" np_thru_hole circle (at -5.1 1.5 90) (size 1.27 1.27) (drill 1.27) (layers *.Cu *.Mask)
+ (solder_mask_margin 0.01) (clearance 0.05) (tstamp bd267e36-48fd-426a-bd26-acc17af20de2))
+ (pad "1" smd rect (at -3.6 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 20 "/A1") (pinfunction "Pin_1") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 5e2a3ac4-b7ae-4de6-be5f-c6047bc3e66b))
+ (pad "2" smd rect (at -3.6 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 10 "/B1") (pinfunction "Pin_2") (solder_mask_margin 0.01) (clearance 0.05) (tstamp e7721210-fa4c-4acb-ae98-8378651cf5c7))
+ (pad "3" smd rect (at -2.8 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 19 "/A2") (pinfunction "Pin_3") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 9dafcdc0-cd27-4659-aab7-921f3b8e14cf))
+ (pad "4" smd rect (at -2.8 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 9 "/B2") (pinfunction "Pin_4") (solder_mask_margin 0.01) (clearance 0.05) (tstamp e80e7a3e-da77-4ce2-ae89-4007dc299c65))
+ (pad "5" smd rect (at -2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 18 "/A3") (pinfunction "Pin_5") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 643014d6-72c2-4f4d-a7c4-bfc7b0b83a06))
+ (pad "6" smd rect (at -2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 8 "/B3") (pinfunction "Pin_6") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 9ae0ba6e-89e4-45e3-8d81-b22a12a3b98d))
+ (pad "7" smd rect (at -1.2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 17 "/A4") (pinfunction "Pin_7") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 3f89cc0f-95ff-4164-822c-1608e975b7e1))
+ (pad "8" smd rect (at -1.2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 7 "/B4") (pinfunction "Pin_8") (solder_mask_margin 0.01) (clearance 0.05) (tstamp ccbde77b-e584-4afa-81f5-deef96c684c8))
+ (pad "9" smd rect (at -0.4 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 16 "/A5") (pinfunction "Pin_9") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 1ffda658-7d6a-434a-88d8-4636bb182c95))
+ (pad "10" smd rect (at -0.4 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 6 "/B5") (pinfunction "Pin_10") (solder_mask_margin 0.01) (clearance 0.05) (tstamp bc35860c-6e2a-402b-a9ae-481432b3e0f6))
+ (pad "11" smd rect (at 0.4 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 15 "/A6") (pinfunction "Pin_11") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 229256d0-aaec-4bb7-b05b-6bc996e5f5bd))
+ (pad "12" smd rect (at 0.4 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 5 "/B6") (pinfunction "Pin_12") (solder_mask_margin 0.01) (clearance 0.05) (tstamp d52acd35-e3bb-4ba5-8c9a-70511c95272e))
+ (pad "13" smd rect (at 1.2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 14 "/A7") (pinfunction "Pin_13") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 53c1cdf6-043a-4bcc-90e1-ad1b6267aeae))
+ (pad "14" smd rect (at 1.2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 4 "/B7") (pinfunction "Pin_14") (solder_mask_margin 0.01) (clearance 0.05) (tstamp eab0e656-0e59-437b-a17b-c4fd04ab0b26))
+ (pad "15" smd rect (at 2 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 13 "/A8") (pinfunction "Pin_15") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 2f020e3b-e6fd-498c-aa29-084f0595ec81))
+ (pad "16" smd rect (at 2 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 3 "/B8") (pinfunction "Pin_16") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 670b9f32-541d-4906-aabb-c9d6f19dac23))
+ (pad "17" smd rect (at 2.8 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 12 "/A9") (pinfunction "Pin_17") (solder_mask_margin 0.01) (clearance 0.05) (tstamp 3848c83f-f022-406e-a190-eea643349fec))
+ (pad "18" smd rect (at 2.8 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 2 "/B9") (pinfunction "Pin_18") (solder_mask_margin 0.01) (clearance 0.05) (tstamp f9d07626-193e-4d25-80e0-95889d31c3f8))
+ (pad "19" smd rect (at 3.6 1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 11 "/A10") (pinfunction "Pin_19") (solder_mask_margin 0.01) (clearance 0.05) (tstamp efadc025-5295-4117-894e-76fc9c77d1a6))
+ (pad "20" smd rect (at 3.6 -1.7 90) (size 0.5 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
+ (net 1 "/B10") (pinfunction "Pin_20") (solder_mask_margin 0.01) (clearance 0.05) (tstamp d103f9d8-ebca-4ad3-a67a-b9d13f8021f6))
+ )
+
+ (module "Connector_PinHeader_2.54mm:PinHeader_2x05_P2.54mm_Vertical" (layer "B.Cu") (tedit 59FED5CC) (tstamp 7e3389eb-1827-4dad-93d7-147fc82f0a9b)
+ (at 150 80.3 90)
+ (descr "Through hole straight pin header, 2x05, 2.54mm pitch, double rows")
+ (tags "Through hole pin header THT 2x05 2.54mm double row")
+ (path "/6b3463ed-6f77-4939-96a8-996fa4157a95")
+ (fp_text reference "J2" (at 1.27 2.33 90) (layer "B.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp ec7abf32-aeb5-4bb7-ba45-2bf4df3d5938)
+ )
+ (fp_text value "Conn_02x05_Odd_Even" (at 1.27 -12.49 90) (layer "B.Fab") hide
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp 0fa26bb7-54fc-4326-96a1-cf513f39ed83)
+ )
+ (fp_text user "${REFERENCE}" (at 1.27 -5.08 180) (layer "B.Fab")
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp 6fef10bb-ed44-4c58-b790-3ee1782b4cc6)
+ )
+ (fp_line (start -1.33 -1.27) (end -1.33 -11.49) (layer "B.SilkS") (width 0.12) (tstamp 1074bce0-d550-4b7f-895d-fd14c8297e5f))
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+ (fp_line (start -1.33 -1.27) (end 1.27 -1.27) (layer "B.SilkS") (width 0.12) (tstamp fbcc76a1-ea92-420f-a313-aedebfdb3f34))
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+ (fp_line (start 0 1.27) (end 3.81 1.27) (layer "B.Fab") (width 0.1) (tstamp 5871cf0a-f48b-4194-8a2f-2721d132c2d0))
+ (fp_line (start -1.27 0) (end 0 1.27) (layer "B.Fab") (width 0.1) (tstamp 7bd76e79-f68a-4d76-b181-2d972eba1d85))
+ (fp_line (start 3.81 -11.43) (end -1.27 -11.43) (layer "B.Fab") (width 0.1) (tstamp 8d0e0701-73a6-46c3-9816-a55cbd07843a))
+ (fp_line (start -1.27 -11.43) (end -1.27 0) (layer "B.Fab") (width 0.1) (tstamp be61eaa2-bd6d-48d5-8028-e1197e5309f3))
+ (pad "1" thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (remove_unused_layers) (keep_end_layers)
+ (net 20 "/A1") (pinfunction "Pin_1") (tstamp 45b42be2-cea1-47b2-8879-272ff0e7abf4))
+ (pad "2" thru_hole oval (at 2.54 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (remove_unused_layers) (keep_end_layers)
+ (net 19 "/A2") (pinfunction "Pin_2") (tstamp e0fb7058-f546-4279-9ec6-99b74ea8c3fa))
+ (pad "3" thru_hole oval (at 0 -2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (remove_unused_layers) (keep_end_layers)
+ (net 18 "/A3") (pinfunction "Pin_3") (tstamp 4beb6792-07bf-472b-ad1d-8017cf9b498c))
+ (pad "4" thru_hole oval (at 2.54 -2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 17 "/A4") (pinfunction "Pin_4") (tstamp 7a58c48b-1306-417e-9b55-8350ecd70605))
+ (pad "5" thru_hole oval (at 0 -5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 16 "/A5") (pinfunction "Pin_5") (tstamp beb08ce1-9ce1-4ee8-b81b-30c89cba792e))
+ (pad "6" thru_hole oval (at 2.54 -5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 15 "/A6") (pinfunction "Pin_6") (tstamp 9c632be4-bd26-47f8-b8db-1fdb3a5193e3))
+ (pad "7" thru_hole oval (at 0 -7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 14 "/A7") (pinfunction "Pin_7") (tstamp dfe0ca30-6633-4e05-976f-7cb2462cf2ad))
+ (pad "8" thru_hole oval (at 2.54 -7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 13 "/A8") (pinfunction "Pin_8") (tstamp 0e81ecb6-8a2d-49ac-9629-61448914cf4c))
+ (pad "9" thru_hole oval (at 0 -10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 12 "/A9") (pinfunction "Pin_9") (tstamp aa6c8b71-14c5-4b37-862e-0ae5079b6250))
+ (pad "10" thru_hole oval (at 2.54 -10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 11 "/A10") (pinfunction "Pin_10") (tstamp a0fad4a0-f214-4b40-8faa-d3e39c29b893))
+ (model "${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x05_P2.54mm_Vertical.wrl"
+ (offset (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module "Connector_PinHeader_2.54mm:PinHeader_2x05_P2.54mm_Vertical" (layer "B.Cu") (tedit 59FED5CC) (tstamp a843ead7-b140-4625-b0b5-a62fd60cd038)
+ (at 149.9 100.5 90)
+ (descr "Through hole straight pin header, 2x05, 2.54mm pitch, double rows")
+ (tags "Through hole pin header THT 2x05 2.54mm double row")
+ (path "/11c51f8e-2d37-4686-bde5-822593c1e251")
+ (fp_text reference "J1" (at 1.27 2.33 90) (layer "B.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp f3519a5d-4e31-481e-b6e7-216578eb599a)
+ )
+ (fp_text value "Conn_02x05_Odd_Even" (at 1.27 -12.49 90) (layer "B.Fab") hide
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp 3ef2f5a0-6974-442e-9ae9-7b0f3f70a808)
+ )
+ (fp_text user "${REFERENCE}" (at 1.27 -5.08 180) (layer "B.Fab")
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ (tstamp 0a1cf444-7276-4fcf-b195-7d23c555e508)
+ )
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diff --git a/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_prl b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_prl
new file mode 100644
index 0000000..e39594a
--- /dev/null
+++ b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_prl
@@ -0,0 +1,68 @@
+{
+ "board": {
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+ "active_layer_preset": "",
+ "hidden_nets": [],
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+ },
+ "selection_filter": {
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+ "graphics": true,
+ "keepouts": true,
+ "lockedItems": true,
+ "otherItems": true,
+ "pads": true,
+ "text": true,
+ "tracks": true,
+ "vias": true,
+ "zones": true
+ },
+ "visible_items": [
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+ ],
+ "visible_layers": "3ffff_80000001"
+ },
+ "meta": {
+ "filename": "dbg_connect_cable.kicad_prl",
+ "version": 2
+ }
+}
diff --git a/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pro b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pro
new file mode 100644
index 0000000..8fa011d
--- /dev/null
+++ b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_pro
@@ -0,0 +1,367 @@
+{
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+ "solder_paste_margin_ratio": -0.0
+ },
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+ 0.4
+ ],
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+ }
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+ },
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+ },
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+ },
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+ "multiple_net_names": "error",
+ "net_not_bus_member": "error",
+ "no_connect_connected": "error",
+ "no_connect_dangling": "error",
+ "pin_not_connected": "error",
+ "pin_not_driven": "error",
+ "pin_to_pin": "warning",
+ "similar_labels": "error",
+ "unresolved_variable": "error"
+ }
+ },
+ "libraries": {
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+ }
+ ],
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+ },
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+ },
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+ },
+ "page_layout_descr_file": ""
+ },
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+ "default_junction_size": 40.0,
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+ "default_text_size": 50.0,
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+ "field_names": [],
+ "pin_symbol_size": 25.0,
+ "text_offset_ratio": 0.3
+ },
+ "legacy_lib_dir": "",
+ "legacy_lib_list": [],
+ "meta": {
+ "version": 0
+ },
+ "net_format_name": "",
+ "page_layout_descr_file": "",
+ "plot_directory": "",
+ "spice_adjust_passive_values": false,
+ "spice_external_command": "spice \"%I\"",
+ "subpart_first_id": 65,
+ "subpart_id_separator": 0
+ },
+ "sheets": [
+ [
+ "9a74d9a3-2539-4212-aa6c-7cc531762e01",
+ ""
+ ]
+ ],
+ "text_variables": {}
+}
diff --git a/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_sch b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_sch
new file mode 100644
index 0000000..ed514e2
--- /dev/null
+++ b/cable/dbg_connect_cable_90/dbg_connect_cable.kicad_sch
@@ -0,0 +1,580 @@
+(kicad_sch (version 20200714) (host eeschema "(5.99.0-2820-g96f4e8f6f)")
+
+ (page 1 1)
+
+ (paper "A4")
+
+ (lib_symbols
+ (symbol "Connector_Generic:Conn_02x05_Odd_Even" (pin_names hide)
+ (property "Reference" "J" (id 0) (at 1.27 7.62 0)
+ (effects (font (size 1.27 1.27)))
+ )
+ (property "Value" "Conn_02x05_Odd_Even" (id 1) (at 1.27 -7.62 0)
+ (effects (font (size 1.27 1.27)))
+ )
+ (property "Footprint" "" (id 2) (at 0 0 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (property "Datasheet" "~" (id 3) (at 0 0 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (property "ki_keywords" "connector" (id 4) (at 0 0 0)
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diff --git a/cable/dbg_connect_cable_90/fp-info-cache b/cable/dbg_connect_cable_90/fp-info-cache
new file mode 100644
index 0000000..5954164
--- /dev/null
+++ b/cable/dbg_connect_cable_90/fp-info-cache
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new file mode 100644
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new file mode 100644
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new file mode 100644
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new file mode 100644
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diff --git a/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Mask.gbr b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Mask.gbr
new file mode 100644
index 0000000..39f4b62
--- /dev/null
+++ b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Mask.gbr
@@ -0,0 +1,531 @@
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diff --git a/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Paste.gbr b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Paste.gbr
new file mode 100644
index 0000000..c54ae1a
--- /dev/null
+++ b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_Paste.gbr
@@ -0,0 +1,39 @@
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diff --git a/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_SilkS.gbr b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_SilkS.gbr
new file mode 100644
index 0000000..7a8222f
--- /dev/null
+++ b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-F_SilkS.gbr
@@ -0,0 +1,49 @@
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diff --git a/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-NPTH.drl b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-NPTH.drl
new file mode 100644
index 0000000..9bd1d6b
--- /dev/null
+++ b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-NPTH.drl
@@ -0,0 +1,17 @@
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+; FORMAT={-:-/ absolute / inch / decimal}
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+; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.99.0-2820-g96f4e8f6f)
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diff --git a/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-PTH.drl b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-PTH.drl
new file mode 100644
index 0000000..9723ba4
--- /dev/null
+++ b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-PTH.drl
@@ -0,0 +1,42 @@
+M48
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+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2020-10-02T17:31:39+02:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.99.0-2820-g96f4e8f6f)
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diff --git a/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-job.gbrjob b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-job.gbrjob
new file mode 100644
index 0000000..60292c2
--- /dev/null
+++ b/cable/dbg_connect_cable_90/gerber/dbg_connect_cable-job.gbrjob
@@ -0,0 +1,127 @@
+{
+ "Header": {
+ "GenerationSoftware": {
+ "Vendor": "KiCad",
+ "Application": "Pcbnew",
+ "Version": "(5.99.0-2820-g96f4e8f6f)"
+ },
+ "CreationDate": "2020-10-02T17:31:37+02:00"
+ },
+ "GeneralSpecs": {
+ "ProjectId": {
+ "Name": "dbg_connect_cable",
+ "GUID": "6462675f-636f-46e6-9e65-63745f636162",
+ "Revision": "rev?"
+ },
+ "Size": {
+ "X": 18.1,
+ "Y": 28.1
+ },
+ "LayerNumber": 2,
+ "BoardThickness": 1.6,
+ "Finish": "None"
+ },
+ "DesignRules": [
+ {
+ "Layers": "Outer",
+ "PadToPad": 0.05,
+ "PadToTrack": 0.05,
+ "TrackToTrack": 0.2,
+ "MinLineWidth": 0.4
+ }
+ ],
+ "FilesAttributes": [
+ {
+ "Path": "dbg_connect_cable-F_Cu.gbr",
+ "FileFunction": "Copper,L1,Top",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-B_Cu.gbr",
+ "FileFunction": "Copper,L2,Bot",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-F_Paste.gbr",
+ "FileFunction": "SolderPaste,Top",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-B_Paste.gbr",
+ "FileFunction": "SolderPaste,Bot",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-F_SilkS.gbr",
+ "FileFunction": "Legend,Top",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-B_SilkS.gbr",
+ "FileFunction": "Legend,Bot",
+ "FilePolarity": "Positive"
+ },
+ {
+ "Path": "dbg_connect_cable-F_Mask.gbr",
+ "FileFunction": "SolderMask,Top",
+ "FilePolarity": "Negative"
+ },
+ {
+ "Path": "dbg_connect_cable-B_Mask.gbr",
+ "FileFunction": "SolderMask,Bot",
+ "FilePolarity": "Negative"
+ },
+ {
+ "Path": "dbg_connect_cable-Edge_Cuts.gbr",
+ "FileFunction": "Profile",
+ "FilePolarity": "Positive"
+ }
+ ],
+ "MaterialStackup": [
+ {
+ "Type": "Legend",
+ "Name": "Top Silk Screen"
+ },
+ {
+ "Type": "SolderPaste",
+ "Name": "Top Solder Paste"
+ },
+ {
+ "Type": "SolderMask",
+ "Color": "Green",
+ "Thickness": 0.01,
+ "Name": "Top Solder Mask"
+ },
+ {
+ "Type": "Copper",
+ "Thickness": 0.035,
+ "Name": "F.Cu"
+ },
+ {
+ "Type": "Dielectric",
+ "Thickness": 1.51,
+ "Material": "FR4",
+ "Name": "F.Cu/B.Cu",
+ "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
+ },
+ {
+ "Type": "Copper",
+ "Thickness": 0.035,
+ "Name": "B.Cu"
+ },
+ {
+ "Type": "SolderMask",
+ "Color": "Green",
+ "Thickness": 0.01,
+ "Name": "Bottom Solder Mask"
+ },
+ {
+ "Type": "SolderPaste",
+ "Name": "Bottom Solder Paste"
+ },
+ {
+ "Type": "Legend",
+ "Name": "Bottom Silk Screen"
+ }
+ ]
+}
diff --git a/common/common_footprints.pretty/EPT_EC.8_20pin.kicad_mod b/common/common_footprints.pretty/EPT_EC.8_20pin.kicad_mod
new file mode 100644
index 0000000..f552e98
--- /dev/null
+++ b/common/common_footprints.pretty/EPT_EC.8_20pin.kicad_mod
@@ -0,0 +1,55 @@
+(module "EPT_EC.8_20pin" (layer F.Cu) (tedit 5F774092)
+ (fp_text reference "REF**" (at -6.3 -4.4 unlocked) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)) (justify left))
+ (tstamp 4e289679-ef08-40ee-8053-ab5692e5956e)
+ )
+ (fp_text value "EPT_EC.8_20pin" (at 0 4.6 unlocked) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp a211d781-28c2-422c-aad4-be94b0690e2f)
+ )
+ (fp_rect (start -6.3 -3.5) (end 6.3 3.5) (layer F.SilkS) (width 0.2) (tstamp f1562401-ee68-41cc-a8ae-78fb7c553782))
+ (pad "" np_thru_hole circle (at 5.2 0) (size 1.27 1.27) (drill 1.27) (layers *.Cu *.Mask)
+ (solder_mask_margin 0.01) (clearance 0.05) (tstamp c5a49d1d-3fed-446a-94ae-df6875d00938))
+ (pad "" np_thru_hole circle (at -5.1 1.5) (size 1.27 1.27) (drill 1.27) (layers *.Cu *.Mask)
+ (solder_mask_margin 0.01) (clearance 0.05) (tstamp cb8eb9e8-dbeb-4587-a5ef-0f4f5f3ae6e9))
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generated by cgit (git 2.34.1) at 2024-05-03 06:20:37 +0000