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| author | jaseg <git@jaseg.net> | 2019-01-13 01:35:03 +0900 |
|---|---|---|
| committer | jaseg <git@jaseg.net> | 2019-01-13 01:35:03 +0900 |
| commit | 7b5ca8102b10009b305a5b5c3e1978cb351858c5 (patch) | |
| tree | 56a1036e2b249f7c17776c639088d123cb1c3072 /fw/adc.c | |
| parent | 6006b360d1211283165d684ea9b09a5ea63510a7 (diff) | |
| download | 8seg-7b5ca8102b10009b305a5b5c3e1978cb351858c5.tar.gz 8seg-7b5ca8102b10009b305a5b5c3e1978cb351858c5.tar.bz2 8seg-7b5ca8102b10009b305a5b5c3e1978cb351858c5.zip | |
Basic timer-based blanking working
Diffstat (limited to 'fw/adc.c')
| -rw-r--r-- | fw/adc.c | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -140,7 +140,7 @@ static void adc_dma_init(int burstlen, bool enable_interrupt) { if (enable_interrupt) { /* triggered on transfer completion. We use this to process the ADC data */ NVIC_EnableIRQ(DMA1_Channel1_IRQn); - NVIC_SetPriority(DMA1_Channel1_IRQn, 3<<5); + NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5); } else { NVIC_DisableIRQ(DMA1_Channel1_IRQn); DMA1->IFCR |= DMA_IFCR_CGIF1; @@ -208,12 +208,15 @@ void bit_detector(struct bit_detector_st *st, int a) { new_bit = 0; else if (diff > st->hysteresis_mv/2) new_bit = 1; + else + blank(); st->len_ctr++; if (new_bit != st->last_bit) { st->last_bit = new_bit; st->len_ctr = 0; st->committed_len_ctr = st->base_interval_cycles>>1; + unblank(new_bit); } else if (st->len_ctr >= st->committed_len_ctr) { st->committed_len_ctr += st->base_interval_cycles; |