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author | jaseg <git@jaseg.net> | 2019-01-13 01:35:03 +0900 |
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committer | jaseg <git@jaseg.net> | 2019-01-13 01:35:03 +0900 |
commit | 7b5ca8102b10009b305a5b5c3e1978cb351858c5 (patch) | |
tree | 56a1036e2b249f7c17776c639088d123cb1c3072 /fw | |
parent | 6006b360d1211283165d684ea9b09a5ea63510a7 (diff) | |
download | 8seg-7b5ca8102b10009b305a5b5c3e1978cb351858c5.tar.gz 8seg-7b5ca8102b10009b305a5b5c3e1978cb351858c5.tar.bz2 8seg-7b5ca8102b10009b305a5b5c3e1978cb351858c5.zip |
Basic timer-based blanking working
Diffstat (limited to 'fw')
-rw-r--r-- | fw/adc.c | 5 | ||||
-rw-r--r-- | fw/adc.h | 3 | ||||
-rw-r--r-- | fw/main.c | 69 |
3 files changed, 54 insertions, 23 deletions
@@ -140,7 +140,7 @@ static void adc_dma_init(int burstlen, bool enable_interrupt) { if (enable_interrupt) { /* triggered on transfer completion. We use this to process the ADC data */ NVIC_EnableIRQ(DMA1_Channel1_IRQn); - NVIC_SetPriority(DMA1_Channel1_IRQn, 3<<5); + NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5); } else { NVIC_DisableIRQ(DMA1_Channel1_IRQn); DMA1->IFCR |= DMA_IFCR_CGIF1; @@ -208,12 +208,15 @@ void bit_detector(struct bit_detector_st *st, int a) { new_bit = 0; else if (diff > st->hysteresis_mv/2) new_bit = 1; + else + blank(); st->len_ctr++; if (new_bit != st->last_bit) { st->last_bit = new_bit; st->len_ctr = 0; st->committed_len_ctr = st->base_interval_cycles>>1; + unblank(new_bit); } else if (st->len_ctr >= st->committed_len_ctr) { st->committed_len_ctr += st->base_interval_cycles; @@ -90,4 +90,7 @@ void adc_configure_monitor_mode(struct command_if_def *cmd_if, int ivl_us); void bit_detector(struct bit_detector_st *st, int a); void receive_bit(struct bit_detector_st *st, int bit); +void blank(void); +void unblank(int new_bit); + #endif/*__ADC_H__*/ @@ -44,6 +44,12 @@ struct { [PKT_TYPE_SET_OUTPUTS] = 8 } }; +void set_drv_gpios(uint8_t val) { + int a=!!(val&1), b=!!(val&2), c=!!(val&4), d=!!(val&8); + GPIOA->ODR &= ~(!a<<3 | !b<<7 | c<<6 | d<<4); + GPIOA->ODR |= a<<3 | b<<7 | !c<<6 | !d<<4; +} + uint8_t out_state = 0x01; void set_outputs(uint8_t val[8]) { /* TODO implement BCM for digital brightness control */ @@ -61,6 +67,46 @@ void set_outputs_binary(int mask, int global_brightness) { set_outputs(val); } +void blank(void) { + set_drv_gpios(0); +} + +int bit; /* FIXME */ +void unblank(int new_bit) { + bit = new_bit; + NVIC_EnableIRQ(TIM3_IRQn); + NVIC_SetPriority(TIM3_IRQn, 3<<5); + + TIM3->DIER &= (~TIM_DIER_UIE) & (~TIM_DIER_CC4IE); + + TIM3->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */ + TIM3->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */ + + TIM3->CCR4 = 50; /* Trigger towards start of timer cycle */ + TIM3->PSC = 48-1; + TIM3->ARR = 400-1; + + TIM3->EGR |= TIM_EGR_UG; + TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM; + TIM3->SR &= (~TIM_SR_UIF) & (~TIM_SR_CC4IF); + TIM3->DIER |= TIM_DIER_UIE | TIM_DIER_CC4IE; + + TIM3->CR1 |= TIM_CR1_CEN; +} + +void TIM3_IRQHandler(void) { + if (TIM3->SR & TIM_SR_UIF) { + blank(); + } else { + if (bit) + set_drv_gpios(out_state & 0xf); + else + set_drv_gpios(out_state >> 4); + } + + TIM3->SR = 0; +} + void handle_command(int command, uint8_t *args) { static int global_brightness = 0xff; switch (command) { @@ -114,33 +160,12 @@ int main(void) { | (2<<GPIO_OSPEEDR_OSPEEDR6_Pos) /* CH2 */ | (2<<GPIO_OSPEEDR_OSPEEDR7_Pos); /* CH1 */ - void set_drv_gpios(uint8_t val) { - int a=!!(val&1), b=!!(val&2), c=!!(val&4), d=!!(val&8); - GPIOA->ODR &= ~(!a<<3 | !b<<7 | c<<6 | d<<4); - GPIOA->ODR |= a<<3 | b<<7 | !c<<6 | !d<<4; - } set_drv_gpios(0); adc_configure_monitor_mode(&cmd_if.cmd_if, 50 /*us*/); - int debounce_ctr = 0; - int val_last = 0; - int reset_ctr = 0; while (42) { - if (reset_ctr) - reset_ctr--; - else - set_drv_gpios(0); - - int val = adc_state.det_st.last_bit; - if (val != val_last) { - if (val) - set_drv_gpios(out_state & 0xf); - else - set_drv_gpios(out_state >> 4); - reset_ctr = 500; - val_last = val; - } + /* idle */ } } |