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| author | jaseg <git@jaseg.net> | 2018-12-24 19:09:46 +0900 |
|---|---|---|
| committer | jaseg <git@jaseg.net> | 2018-12-24 19:09:46 +0900 |
| commit | f5d7b0428db5257d62c080daa2757199c27ef784 (patch) | |
| tree | 0871ee9b9d75b3d3f0c909d2ab64e989b92cc9d7 /driver_fw | |
| parent | 0029ed768ea0b3626ba8b26c369c409962ff38b6 (diff) | |
| download | 8seg-f5d7b0428db5257d62c080daa2757199c27ef784.tar.gz 8seg-f5d7b0428db5257d62c080daa2757199c27ef784.tar.bz2 8seg-f5d7b0428db5257d62c080daa2757199c27ef784.zip | |
Add untested ADC mode switching code
Diffstat (limited to 'driver_fw')
| -rw-r--r-- | driver_fw/main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/driver_fw/main.c b/driver_fw/main.c index e4960c7..efea9c6 100644 --- a/driver_fw/main.c +++ b/driver_fw/main.c @@ -67,7 +67,7 @@ int main(void) { TIM1->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE; /* Configure output compare unit 1 to PWM mode 1, enable CCR1 preload */ TIM1->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1E; /* Confiugre CH1 to complementary outputs */ - TIM1->BDTR = TIM_BDTR_MOE | 100<<TIM_BDTR_DTG_Pos; /* Enable MOE on next update event, i.e. on initial timer load. + TIM1->BDTR = TIM_BDTR_MOE | (0xc0 | (63-32))<<TIM_BDTR_DTG_Pos; /* Enable MOE on next update event, i.e. on initial timer load. Set dead-time to 100us. */ TIM1->CR1 |= TIM_CR1_CEN; TIM1->ARR = 1000-1; /* Set f=1.0kHz/T=1.0ms */ |