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7seg.git
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7seg: Large display made up of hundreds of 7-segment displays
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fw
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Author
Files
Lines
2018-01-05
Split project into individual source files and add license
jaseg
12
-657
/
+1620
2018-01-05
Firmware directory reorganization
jaseg
30
-93
/
+16
2018-01-05
Add some documentation
jaseg
7
-129
/
+149
2017-12-10
Make status request work, fix uc-side cobs encoding bug
jaseg
2
-53
/
+96
2017-12-10
Prettified the python side of things a bit
jaseg
1
-18
/
+25
2017-12-10
Add discovery and addressing mechanism
jaseg
3
-18
/
+99
2017-12-10
Prettify and document AUX LED handling
jaseg
1
-8
/
+10
2017-12-10
Make comm and error LEDs useful
jaseg
2
-4
/
+33
2017-12-10
ADC temperature measurement works now
jaseg
1
-8
/
+12
2017-12-10
ADC properly triggering now
jaseg
2
-21
/
+63
2017-12-10
Rough ADC triggering works now
jaseg
1
-28
/
+29
2017-12-10
Add lots of doc and fix segment driving
jaseg
3
-46
/
+163
2017-12-09
Framing works now
jaseg
2
-50
/
+66
2017-12-09
Framing experiments
jaseg
2
-2
/
+71
2017-12-09
UART and LEDs playing nicely
jaseg
1
-19
/
+56
2017-12-09
Made all ISRs *fast* (<2.5us)
jaseg
1
-3
/
+8
2017-12-09
Aux register loading further optimized
jaseg
1
-59
/
+55
2017-12-09
Fixed aux cycle
jaseg
1
-50
/
+55
2017-12-09
Cycle timing is fixed again
jaseg
1
-54
/
+76
2017-12-08
Basic UART working, but too slow
jaseg
1
-297
/
+54
2017-09-18
hw v0.4
jaseg
1
-95
/
+177
2017-09-06
Fixes for second prototype (v0.3)
jaseg
1
-3
/
+5
2017-09-02
Temperature/VCC ADC working
jaseg
2
-21
/
+95
2017-09-01
Now with working source extraction from firmware
jaseg
4
-10
/
+18
2017-09-01
Add missing files
jaseg
6
-2
/
+298
2017-09-01
UART magic seems to be working now
jaseg
4
-121
/
+216
2017-09-01
DMA channel assignments redone, basic protocol stuff working
jaseg
3
-34
/
+121
2017-08-24
Serial protocol now working including CRC
jaseg
2
-9
/
+37
2017-08-23
Interrupt-driven SPI1 fundamentally working
jaseg
1
-44
/
+78
2017-08-23
Comms working except for TIM3/SPI1 race
jaseg
2
-6
/
+17
2017-08-23
Add cmsis export generator
jaseg
2
-0
/
+32
2017-08-23
Add transpose test
jaseg
6
-129
/
+280
2017-08-22
Add profiling script
jaseg
2
-0
/
+31
2017-08-15
Benchmark code
jaseg
2
-7
/
+24
2017-08-15
working commit
jaseg
3
-19
/
+60
2017-08-15
Temporary for bit shuffling
jaseg
1
-11
/
+5
2017-08-15
Working on uart code
jaseg
2
-35
/
+147
2017-08-14
Multiplexing is working
jaseg
3
-65
/
+166
2017-08-13
Board rev 0.3 working
jaseg
1
-12
/
+45
2017-07-20
Add missing firmware build files
jaseg
2
-0
/
+286
2017-06-12
Add resistor calculation script
jaseg
1
-22
/
+22
2017-06-11
Test program working
jaseg
1
-30
/
+54
2017-06-10
fw working commit
jaseg
8
-0
/
+802