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AgeCommit message (Expand)AuthorFilesLines
2017-12-09Aux register loading further optimizedjaseg1-59/+55
2017-12-09Fixed aux cyclejaseg1-50/+55
2017-12-09Cycle timing is fixed againjaseg1-54/+76
2017-12-08Basic UART working, but too slowjaseg1-297/+54
2017-09-18hw v0.4jaseg1-95/+177
2017-09-06Fixes for second prototype (v0.3)jaseg1-3/+5
2017-09-02Temperature/VCC ADC workingjaseg1-19/+93
2017-09-01UART magic seems to be working nowjaseg1-108/+195
2017-09-01DMA channel assignments redone, basic protocol stuff workingjaseg1-30/+104
2017-08-24Serial protocol now working including CRCjaseg1-7/+30
2017-08-23Interrupt-driven SPI1 fundamentally workingjaseg1-44/+78
2017-08-23Comms working except for TIM3/SPI1 racejaseg1-5/+15
2017-08-23Add transpose testjaseg1-128/+85
2017-08-15Benchmark codejaseg1-7/+7
2017-08-15working commitjaseg1-17/+57
2017-08-15Temporary for bit shufflingjaseg1-11/+5
2017-08-15Working on uart codejaseg1-35/+146
2017-08-14Multiplexing is workingjaseg1-61/+152
2017-08-13Board rev 0.3 workingjaseg1-12/+45
2017-06-12Add resistor calculation scriptjaseg1-22/+22
2017-06-11Test program workingjaseg1-30/+54
2017-06-10fw working commitjaseg1-0/+98
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