| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-12-09 | Aux register loading further optimized | jaseg | 1 | -59/+55 |
| 2017-12-09 | Fixed aux cycle | jaseg | 1 | -50/+55 |
| 2017-12-09 | Cycle timing is fixed again | jaseg | 1 | -54/+76 |
| 2017-12-08 | Basic UART working, but too slow | jaseg | 1 | -297/+54 |
| 2017-09-18 | hw v0.4 | jaseg | 13 | -2364/+2432 |
| 2017-09-06 | Fix up RS485/digital power label | jaseg | 12 | -77/+1986 |
| 2017-09-06 | Fix up version label and one ground trace | jaseg | 15 | -28917/+29500 |
| 2017-09-06 | Fixes for second prototype (v0.3) | jaseg | 21 | -9154/+10643 |
| 2017-09-02 | Temperature/VCC ADC working | jaseg | 2 | -21/+95 |
| 2017-09-01 | Now with working source extraction from firmware | jaseg | 4 | -10/+18 |
| 2017-09-01 | Add missing files | jaseg | 6 | -2/+298 |
| 2017-09-01 | UART magic seems to be working now | jaseg | 4 | -121/+216 |
| 2017-09-01 | DMA channel assignments redone, basic protocol stuff working | jaseg | 3 | -34/+121 |
| 2017-08-24 | Serial protocol now working including CRC | jaseg | 2 | -9/+37 |
| 2017-08-23 | Interrupt-driven SPI1 fundamentally working | jaseg | 1 | -44/+78 |
| 2017-08-23 | Comms working except for TIM3/SPI1 race | jaseg | 2 | -6/+17 |
| 2017-08-23 | Add cmsis export generator | jaseg | 2 | -0/+32 |
| 2017-08-23 | Add transpose test | jaseg | 6 | -129/+280 |
| 2017-08-22 | Add profiling script | jaseg | 2 | -0/+31 |
| 2017-08-15 | Benchmark code | jaseg | 2 | -7/+24 |
| 2017-08-15 | working commit | jaseg | 3 | -19/+60 |
| 2017-08-15 | Temporary for bit shuffling | jaseg | 1 | -11/+5 |
| 2017-08-15 | Working on uart code | jaseg | 2 | -35/+147 |
| 2017-08-14 | Multiplexing is working | jaseg | 3 | -65/+166 |
| 2017-08-13 | Board rev 0.3 working | jaseg | 1 | -12/+45 |
| 2017-07-21 | Second production run, v0.3 | jaseg | 15 | -8822/+9494 |
| 2017-07-21 | Final silk art positioning | jaseg | 12 | -111925/+111925 |
| 2017-07-20 | Add missing firmware build files | jaseg | 2 | -0/+286 |
| 2017-07-20 | Second board revision | jaseg | 16 | -160767/+167539 |
| 2017-07-15 | Schematic fixed up so far | jaseg | 13 | -3006/+3496 |
| 2017-06-12 | Add resistor calculation script | jaseg | 2 | -22/+149 |
| 2017-06-11 | Test program working | jaseg | 1 | -30/+54 |
| 2017-06-10 | fw working commit | jaseg | 8 | -0/+802 |
| 2017-06-10 | foo | jaseg | 12 | -1689/+1542 |
| 2017-05-17 | Release v0.2 | jaseg | 28 | -17464/+18529 |
| 2017-05-04 | Design mostly done | jaseg | 52 | -4218/+351132 |
| 2017-05-02 | Layout mostly done | jaseg | 10 | -1139/+6297 |
| 2017-04-30 | Foo | jaseg | 6 | -4957/+4778 |
| 2017-04-29 | Pre safety fixup | jaseg | 8 | -1438/+7443 |
| 2017-04-28 | Added protection stuff | jaseg | 5 | -2518/+4612 |
| 2017-04-26 | Initial commit | jaseg | 19 | -0/+12924 |
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index : 7seg.git | |
| 7seg: Large display made up of hundreds of 7-segment displays | jaseg |
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