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2017-12-10Prettified the python side of things a bitjaseg1-18/+25
2017-12-10Add discovery and addressing mechanismjaseg3-18/+99
2017-12-10Prettify and document AUX LED handlingjaseg1-8/+10
2017-12-10Make comm and error LEDs usefuljaseg2-4/+33
2017-12-10ADC temperature measurement works nowjaseg1-8/+12
2017-12-10ADC properly triggering nowjaseg2-21/+63
2017-12-10Rough ADC triggering works nowjaseg1-28/+29
2017-12-10Add lots of doc and fix segment drivingjaseg3-46/+163
2017-12-09Framing works nowjaseg2-50/+66
2017-12-09Framing experimentsjaseg2-2/+71
2017-12-09UART and LEDs playing nicelyjaseg1-19/+56
2017-12-09Made all ISRs *fast* (<2.5us)jaseg1-3/+8
2017-12-09Aux register loading further optimizedjaseg1-59/+55
2017-12-09Fixed aux cyclejaseg1-50/+55
2017-12-09Cycle timing is fixed againjaseg1-54/+76
2017-12-08Basic UART working, but too slowjaseg1-297/+54
2017-09-18hw v0.4jaseg13-2364/+2432
2017-09-06Fix up RS485/digital power labeljaseg12-77/+1986
2017-09-06Fix up version label and one ground tracejaseg15-28917/+29500
2017-09-06Fixes for second prototype (v0.3)jaseg21-9154/+10643
2017-09-02Temperature/VCC ADC workingjaseg2-21/+95
2017-09-01Now with working source extraction from firmwarejaseg4-10/+18
2017-09-01Add missing filesjaseg6-2/+298
2017-09-01UART magic seems to be working nowjaseg4-121/+216
2017-09-01DMA channel assignments redone, basic protocol stuff workingjaseg3-34/+121
2017-08-24Serial protocol now working including CRCjaseg2-9/+37
2017-08-23Interrupt-driven SPI1 fundamentally workingjaseg1-44/+78
2017-08-23Comms working except for TIM3/SPI1 racejaseg2-6/+17
2017-08-23Add cmsis export generatorjaseg2-0/+32
2017-08-23Add transpose testjaseg6-129/+280
2017-08-22Add profiling scriptjaseg2-0/+31
2017-08-15Benchmark codejaseg2-7/+24
2017-08-15working commitjaseg3-19/+60
2017-08-15Temporary for bit shufflingjaseg1-11/+5
2017-08-15Working on uart codejaseg2-35/+147
2017-08-14Multiplexing is workingjaseg3-65/+166
2017-08-13Board rev 0.3 workingjaseg1-12/+45
2017-07-21Second production run, v0.3jaseg15-8822/+9494
2017-07-21Final silk art positioningjaseg12-111925/+111925
2017-07-20Add missing firmware build filesjaseg2-0/+286
2017-07-20Second board revisionjaseg16-160767/+167539
2017-07-15Schematic fixed up so farjaseg13-3006/+3496
2017-06-12Add resistor calculation scriptjaseg2-22/+149
2017-06-11Test program workingjaseg1-30/+54
2017-06-10fw working commitjaseg8-0/+802
2017-06-10foojaseg12-1689/+1542
2017-05-17Release v0.2jaseg28-17464/+18529
2017-05-04Design mostly donejaseg52-4218/+351132
2017-05-02Layout mostly donejaseg10-1139/+6297
2017-04-30Foojaseg6-4957/+4778
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