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| author | jaseg <git@jaseg.net> | 2017-12-09 15:11:41 +0100 |
|---|---|---|
| committer | jaseg <git@jaseg.net> | 2017-12-09 15:11:41 +0100 |
| commit | 58796333b97c50c4ec791a71dfed3b6a9b7d5d6d (patch) | |
| tree | 25d527f5e8aa2d8a82813436b85efcae457946d4 | |
| parent | 6b7518b29f81fcbc49cb6d1680b9c1e22793e270 (diff) | |
| download | 7seg-58796333b97c50c4ec791a71dfed3b6a9b7d5d6d.tar.gz 7seg-58796333b97c50c4ec791a71dfed3b6a9b7d5d6d.tar.bz2 7seg-58796333b97c50c4ec791a71dfed3b6a9b7d5d6d.zip | |
Made all ISRs *fast* (<2.5us)
| -rw-r--r-- | fw/main.c | 11 |
1 files changed, 8 insertions, 3 deletions
@@ -176,11 +176,11 @@ static int active_segment = 0; /* This value is a constant offset added to every bit period to allow for the timer IRQ handler to execute. This is set * empirically using a debugger and a logic analyzer. */ -#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 13 +#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 9 -#define TIMER_CYCLES_BEFORE_LED_STROBE 12 +#define TIMER_CYCLES_BEFORE_LED_STROBE 8 -#define AUX_SPI_PRETRIGGER 20 +#define AUX_SPI_PRETRIGGER 64 /* Defines for brevity */ #define A TIMER_CYCLES_FOR_SPI_TRANSMISSIONS @@ -252,8 +252,11 @@ void cfg_timer3() { } void TIM1_CC_IRQHandler() { + /* This handler takes about 1.5us */ GPIOA->BSRR = GPIO_BSRR_BS_0; // Debug + SPI1->CR1 |= (2<<SPI_CR1_BR_Pos); /* Set baudrate to 12.5MBd for slow-ish 74HC(T)595*/ + active_bit = 0; active_segment++; if (active_segment == NSEGMENTS) { @@ -280,9 +283,11 @@ void TIM1_CC_IRQHandler() { } void TIM3_IRQHandler() { + /* This handler takes about 2.3us */ GPIOA->BSRR = GPIO_BSRR_BS_4; // Debug //TIM3->CR1 &= ~TIM_CR1_CEN_Msk; FIXME + SPI1->CR1 &= ~SPI_CR1_BR_Msk; /* Reset baudrate to 25MBd for fast MBI5026*/ GPIOA->BSRR = GPIO_BSRR_BS_10; /* Note: On boot, multiplexing will start with bit 1 due to the next few lines. This is perfectly ok. */ |