From 58796333b97c50c4ec791a71dfed3b6a9b7d5d6d Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.net>
Date: Sat, 9 Dec 2017 15:11:41 +0100
Subject: Made all ISRs *fast* (<2.5us)

---
 fw/main.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/fw/main.c b/fw/main.c
index adb7f2d..88dfd82 100644
--- a/fw/main.c
+++ b/fw/main.c
@@ -176,11 +176,11 @@ static int active_segment = 0;
 
 /* This value is a constant offset added to every bit period to allow for the timer IRQ handler to execute. This is set
  * empirically using a debugger and a logic analyzer. */
-#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 13
+#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 9
 
-#define TIMER_CYCLES_BEFORE_LED_STROBE 12
+#define TIMER_CYCLES_BEFORE_LED_STROBE 8
 
-#define AUX_SPI_PRETRIGGER 20
+#define AUX_SPI_PRETRIGGER 64
 
 /* Defines for brevity */
 #define A TIMER_CYCLES_FOR_SPI_TRANSMISSIONS
@@ -252,8 +252,11 @@ void cfg_timer3() {
 }
 
 void TIM1_CC_IRQHandler() {
+    /* This handler takes about 1.5us */
     GPIOA->BSRR = GPIO_BSRR_BS_0; // Debug
 
+    SPI1->CR1 |= (2<<SPI_CR1_BR_Pos); /* Set baudrate to 12.5MBd for slow-ish 74HC(T)595*/
+
     active_bit = 0;
     active_segment++;
     if (active_segment == NSEGMENTS) {
@@ -280,9 +283,11 @@ void TIM1_CC_IRQHandler() {
 }
 
 void TIM3_IRQHandler() {
+    /* This handler takes about 2.3us */
     GPIOA->BSRR = GPIO_BSRR_BS_4; // Debug
     //TIM3->CR1 &= ~TIM_CR1_CEN_Msk; FIXME
 
+    SPI1->CR1 &= ~SPI_CR1_BR_Msk; /* Reset baudrate to 25MBd for fast MBI5026*/
     GPIOA->BSRR = GPIO_BSRR_BS_10;
 
     /* Note: On boot, multiplexing will start with bit 1 due to the next few lines. This is perfectly ok. */
-- 
cgit