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Data Structures</h2></td></tr>
<tr class="memitem:structARM__MCI__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#structARM__MCI__STATUS">ARM_MCI_STATUS</a></td></tr>
<tr class="memdesc:structARM__MCI__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">MCI Status. <a href="group__mci__interface__gr.html#structARM__MCI__STATUS">More...</a><br/></td></tr>
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<tr class="memitem:structARM__MCI__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#structARM__MCI__CAPABILITIES">ARM_MCI_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__MCI__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">MCI Driver Capabilities. <a href="group__mci__interface__gr.html#structARM__MCI__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="memitem:structARM__DRIVER__MCI"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#structARM__DRIVER__MCI">ARM_DRIVER_MCI</a></td></tr>
<tr class="memdesc:structARM__DRIVER__MCI"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the MCI Driver. <a href="group__mci__interface__gr.html#structARM__DRIVER__MCI">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ac1863acc4889811dc5f45ec0e059d892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#ac1863acc4889811dc5f45ec0e059d892">ARM_MCI_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td></tr>
<tr class="separator:ac1863acc4889811dc5f45ec0e059d892"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a125bb871e85f4646ff0fa8be1ab7c8c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#a125bb871e85f4646ff0fa8be1ab7c8c9">ARM_MCI_RESPONSE_Pos</a>   0</td></tr>
<tr class="separator:a125bb871e85f4646ff0fa8be1ab7c8c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af12ae94785114eb31b1e077d52eda3fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#af12ae94785114eb31b1e077d52eda3fd">ARM_MCI_RESPONSE_Msk</a>   (3UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="separator:af12ae94785114eb31b1e077d52eda3fd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga70934cef80884e8c75fb4eebf8452118"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga70934cef80884e8c75fb4eebf8452118">ARM_MCI_RESPONSE_NONE</a>   (0UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:ga70934cef80884e8c75fb4eebf8452118"><td class="mdescLeft"> </td><td class="mdescRight">No response expected (default) <a href="group__mci__send__command__flags__ctrls.html#ga70934cef80884e8c75fb4eebf8452118">More...</a><br/></td></tr>
<tr class="separator:ga70934cef80884e8c75fb4eebf8452118"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa5ddf1cf772b234e3c247039effd0e7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gaa5ddf1cf772b234e3c247039effd0e7b">ARM_MCI_RESPONSE_SHORT</a>   (1UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:gaa5ddf1cf772b234e3c247039effd0e7b"><td class="mdescLeft"> </td><td class="mdescRight">Short response (48-bit) <a href="group__mci__send__command__flags__ctrls.html#gaa5ddf1cf772b234e3c247039effd0e7b">More...</a><br/></td></tr>
<tr class="separator:gaa5ddf1cf772b234e3c247039effd0e7b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa1d541b0edf32ec05e68d623c727ef9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gaa1d541b0edf32ec05e68d623c727ef9c">ARM_MCI_RESPONSE_SHORT_BUSY</a>   (2UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:gaa1d541b0edf32ec05e68d623c727ef9c"><td class="mdescLeft"> </td><td class="mdescRight">Short response with busy signal (48-bit) <a href="group__mci__send__command__flags__ctrls.html#gaa1d541b0edf32ec05e68d623c727ef9c">More...</a><br/></td></tr>
<tr class="separator:gaa1d541b0edf32ec05e68d623c727ef9c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac49c7b39a7c51bd2193e048835bec2fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gac49c7b39a7c51bd2193e048835bec2fb">ARM_MCI_RESPONSE_LONG</a>   (3UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:gac49c7b39a7c51bd2193e048835bec2fb"><td class="mdescLeft"> </td><td class="mdescRight">Long response (136-bit) <a href="group__mci__send__command__flags__ctrls.html#gac49c7b39a7c51bd2193e048835bec2fb">More...</a><br/></td></tr>
<tr class="separator:gac49c7b39a7c51bd2193e048835bec2fb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga497abf878c6e12f54cc7ddb92da76c4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga497abf878c6e12f54cc7ddb92da76c4a">ARM_MCI_RESPONSE_INDEX</a>   (1UL << 2)</td></tr>
<tr class="memdesc:ga497abf878c6e12f54cc7ddb92da76c4a"><td class="mdescLeft"> </td><td class="mdescRight">Check command index in response. <a href="group__mci__send__command__flags__ctrls.html#ga497abf878c6e12f54cc7ddb92da76c4a">More...</a><br/></td></tr>
<tr class="separator:ga497abf878c6e12f54cc7ddb92da76c4a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de">ARM_MCI_RESPONSE_CRC</a>   (1UL << 3)</td></tr>
<tr class="memdesc:ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de"><td class="mdescLeft"> </td><td class="mdescRight">Check CRC in response. <a href="group__mci__send__command__flags__ctrls.html#ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de">More...</a><br/></td></tr>
<tr class="separator:ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga68e879799bb27a1b13baf57ed19d719d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga68e879799bb27a1b13baf57ed19d719d">ARM_MCI_WAIT_BUSY</a>   (1UL << 4)</td></tr>
<tr class="memdesc:ga68e879799bb27a1b13baf57ed19d719d"><td class="mdescLeft"> </td><td class="mdescRight">Wait until busy before sending the command. <a href="group__mci__send__command__flags__ctrls.html#ga68e879799bb27a1b13baf57ed19d719d">More...</a><br/></td></tr>
<tr class="separator:ga68e879799bb27a1b13baf57ed19d719d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8aa566f69aa74ed416213df6ca3267bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga8aa566f69aa74ed416213df6ca3267bd">ARM_MCI_TRANSFER_DATA</a>   (1UL << 5)</td></tr>
<tr class="memdesc:ga8aa566f69aa74ed416213df6ca3267bd"><td class="mdescLeft"> </td><td class="mdescRight">Activate Data transfer. <a href="group__mci__send__command__flags__ctrls.html#ga8aa566f69aa74ed416213df6ca3267bd">More...</a><br/></td></tr>
<tr class="separator:ga8aa566f69aa74ed416213df6ca3267bd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga81606bd94ce782e2c3764b913f929f60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga81606bd94ce782e2c3764b913f929f60">ARM_MCI_CARD_INITIALIZE</a>   (1UL << 6)</td></tr>
<tr class="memdesc:ga81606bd94ce782e2c3764b913f929f60"><td class="mdescLeft"> </td><td class="mdescRight">Execute Memory Card initialization sequence. <a href="group__mci__send__command__flags__ctrls.html#ga81606bd94ce782e2c3764b913f929f60">More...</a><br/></td></tr>
<tr class="separator:ga81606bd94ce782e2c3764b913f929f60"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab2bfeedf1dc2df1872ebbcc559a7385a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gab2bfeedf1dc2df1872ebbcc559a7385a">ARM_MCI_INTERRUPT_COMMAND</a>   (1UL << 7)</td></tr>
<tr class="memdesc:gab2bfeedf1dc2df1872ebbcc559a7385a"><td class="mdescLeft"> </td><td class="mdescRight">Send Interrupt command (CMD40 - MMC only) <a href="group__mci__send__command__flags__ctrls.html#gab2bfeedf1dc2df1872ebbcc559a7385a">More...</a><br/></td></tr>
<tr class="separator:gab2bfeedf1dc2df1872ebbcc559a7385a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc31b6b26988998c84c92a9a698fd5dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gabc31b6b26988998c84c92a9a698fd5dc">ARM_MCI_INTERRUPT_RESPONSE</a>   (1UL << 8)</td></tr>
<tr class="memdesc:gabc31b6b26988998c84c92a9a698fd5dc"><td class="mdescLeft"> </td><td class="mdescRight">Send Interrupt response (CMD40 - MMC only) <a href="group__mci__send__command__flags__ctrls.html#gabc31b6b26988998c84c92a9a698fd5dc">More...</a><br/></td></tr>
<tr class="separator:gabc31b6b26988998c84c92a9a698fd5dc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae04254f51dfd9838583206cae0a5f8f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gae04254f51dfd9838583206cae0a5f8f7">ARM_MCI_BOOT_OPERATION</a>   (1UL << 9)</td></tr>
<tr class="memdesc:gae04254f51dfd9838583206cae0a5f8f7"><td class="mdescLeft"> </td><td class="mdescRight">Execute Boot operation (MMC only) <a href="group__mci__send__command__flags__ctrls.html#gae04254f51dfd9838583206cae0a5f8f7">More...</a><br/></td></tr>
<tr class="separator:gae04254f51dfd9838583206cae0a5f8f7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga30bd304652d4f870ee7ce61c266a9348"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga30bd304652d4f870ee7ce61c266a9348">ARM_MCI_BOOT_ALTERNATIVE</a>   (1UL << 10)</td></tr>
<tr class="memdesc:ga30bd304652d4f870ee7ce61c266a9348"><td class="mdescLeft"> </td><td class="mdescRight">Execute Alternative Boot operation (MMC only) <a href="group__mci__send__command__flags__ctrls.html#ga30bd304652d4f870ee7ce61c266a9348">More...</a><br/></td></tr>
<tr class="separator:ga30bd304652d4f870ee7ce61c266a9348"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8c55bc0a310630d49810802ccd1bb10d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga8c55bc0a310630d49810802ccd1bb10d">ARM_MCI_BOOT_ACK</a>   (1UL << 11)</td></tr>
<tr class="memdesc:ga8c55bc0a310630d49810802ccd1bb10d"><td class="mdescLeft"> </td><td class="mdescRight">Expect Boot Acknowledge (MMC only) <a href="group__mci__send__command__flags__ctrls.html#ga8c55bc0a310630d49810802ccd1bb10d">More...</a><br/></td></tr>
<tr class="separator:ga8c55bc0a310630d49810802ccd1bb10d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab9df5169b37621764f8bb0f93db5281a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gab9df5169b37621764f8bb0f93db5281a">ARM_MCI_CCSD</a>   (1UL << 12)</td></tr>
<tr class="memdesc:gab9df5169b37621764f8bb0f93db5281a"><td class="mdescLeft"> </td><td class="mdescRight">Send Command Completion Signal Disable (CCSD) for CE-ATA device. <a href="group__mci__send__command__flags__ctrls.html#gab9df5169b37621764f8bb0f93db5281a">More...</a><br/></td></tr>
<tr class="separator:gab9df5169b37621764f8bb0f93db5281a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab82c472e4ca3fca12ae3291e25997f00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gab82c472e4ca3fca12ae3291e25997f00">ARM_MCI_CCS</a>   (1UL << 13)</td></tr>
<tr class="memdesc:gab82c472e4ca3fca12ae3291e25997f00"><td class="mdescLeft"> </td><td class="mdescRight">Expect Command Completion Signal (CCS) for CE-ATA device. <a href="group__mci__send__command__flags__ctrls.html#gab82c472e4ca3fca12ae3291e25997f00">More...</a><br/></td></tr>
<tr class="separator:gab82c472e4ca3fca12ae3291e25997f00"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa6f3be235a9dce5c66be8fe64f399846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#gaa6f3be235a9dce5c66be8fe64f399846">ARM_MCI_TRANSFER_READ</a>   (0UL << 0)</td></tr>
<tr class="memdesc:gaa6f3be235a9dce5c66be8fe64f399846"><td class="mdescLeft"> </td><td class="mdescRight">Data Read Transfer (from MCI) <a href="group__mci__transfer__ctrls.html#gaa6f3be235a9dce5c66be8fe64f399846">More...</a><br/></td></tr>
<tr class="separator:gaa6f3be235a9dce5c66be8fe64f399846"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaddc60aab15f75993a99f98f71ddbd50c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#gaddc60aab15f75993a99f98f71ddbd50c">ARM_MCI_TRANSFER_WRITE</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gaddc60aab15f75993a99f98f71ddbd50c"><td class="mdescLeft"> </td><td class="mdescRight">Data Write Transfer (to MCI) <a href="group__mci__transfer__ctrls.html#gaddc60aab15f75993a99f98f71ddbd50c">More...</a><br/></td></tr>
<tr class="separator:gaddc60aab15f75993a99f98f71ddbd50c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4ced782e7c0c70d5f0edbddd1e48323b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#ga4ced782e7c0c70d5f0edbddd1e48323b">ARM_MCI_TRANSFER_BLOCK</a>   (0UL << 1)</td></tr>
<tr class="memdesc:ga4ced782e7c0c70d5f0edbddd1e48323b"><td class="mdescLeft"> </td><td class="mdescRight">Block Data transfer (default) <a href="group__mci__transfer__ctrls.html#ga4ced782e7c0c70d5f0edbddd1e48323b">More...</a><br/></td></tr>
<tr class="separator:ga4ced782e7c0c70d5f0edbddd1e48323b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac7db0cffd571e60758627d889ba7a432"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#gac7db0cffd571e60758627d889ba7a432">ARM_MCI_TRANSFER_STREAM</a>   (1UL << 1)</td></tr>
<tr class="memdesc:gac7db0cffd571e60758627d889ba7a432"><td class="mdescLeft"> </td><td class="mdescRight">Stream Data transfer (MMC only) <a href="group__mci__transfer__ctrls.html#gac7db0cffd571e60758627d889ba7a432">More...</a><br/></td></tr>
<tr class="separator:gac7db0cffd571e60758627d889ba7a432"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7f982d2e5aec768307d35a83c65fb3ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga7f982d2e5aec768307d35a83c65fb3ef">ARM_MCI_BUS_SPEED</a>   (0x01)</td></tr>
<tr class="memdesc:ga7f982d2e5aec768307d35a83c65fb3ef"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s. <a href="group__mci__mode__ctrls.html#ga7f982d2e5aec768307d35a83c65fb3ef">More...</a><br/></td></tr>
<tr class="separator:ga7f982d2e5aec768307d35a83c65fb3ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf7ede525eabc618fbbb9f7a294c8ed96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gaf7ede525eabc618fbbb9f7a294c8ed96">ARM_MCI_BUS_SPEED_MODE</a>   (0x02)</td></tr>
<tr class="memdesc:gaf7ede525eabc618fbbb9f7a294c8ed96"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Speed Mode as specified with arg. <a href="group__mci__mode__ctrls.html#gaf7ede525eabc618fbbb9f7a294c8ed96">More...</a><br/></td></tr>
<tr class="separator:gaf7ede525eabc618fbbb9f7a294c8ed96"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8b7571e37520c07d8ef4f697f3886715"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga8b7571e37520c07d8ef4f697f3886715">ARM_MCI_BUS_CMD_MODE</a>   (0x03)</td></tr>
<tr class="memdesc:ga8b7571e37520c07d8ef4f697f3886715"><td class="mdescLeft"> </td><td class="mdescRight">Set CMD Line Mode as specified with arg. <a href="group__mci__mode__ctrls.html#ga8b7571e37520c07d8ef4f697f3886715">More...</a><br/></td></tr>
<tr class="separator:ga8b7571e37520c07d8ef4f697f3886715"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga876d964d0eeacdb16e93f7558a544587"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga876d964d0eeacdb16e93f7558a544587">ARM_MCI_BUS_DATA_WIDTH</a>   (0x04)</td></tr>
<tr class="memdesc:ga876d964d0eeacdb16e93f7558a544587"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Data Width as specified with arg. <a href="group__mci__mode__ctrls.html#ga876d964d0eeacdb16e93f7558a544587">More...</a><br/></td></tr>
<tr class="separator:ga876d964d0eeacdb16e93f7558a544587"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga78068f519139f2ae7b09e0608070aaf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga78068f519139f2ae7b09e0608070aaf6">ARM_MCI_DRIVER_STRENGTH</a>   (0x05)</td></tr>
<tr class="memdesc:ga78068f519139f2ae7b09e0608070aaf6"><td class="mdescLeft"> </td><td class="mdescRight">Set SD UHS-I Driver Strength as specified with arg. <a href="group__mci__mode__ctrls.html#ga78068f519139f2ae7b09e0608070aaf6">More...</a><br/></td></tr>
<tr class="separator:ga78068f519139f2ae7b09e0608070aaf6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga21e403e8c3fa8cc75431a513813f0a16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga21e403e8c3fa8cc75431a513813f0a16">ARM_MCI_CONTROL_RESET</a>   (0x06)</td></tr>
<tr class="memdesc:ga21e403e8c3fa8cc75431a513813f0a16"><td class="mdescLeft"> </td><td class="mdescRight">Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active. <a href="group__mci__mode__ctrls.html#ga21e403e8c3fa8cc75431a513813f0a16">More...</a><br/></td></tr>
<tr class="separator:ga21e403e8c3fa8cc75431a513813f0a16"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga889473fbfbdcb89aab4d53cc8a13f615"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga889473fbfbdcb89aab4d53cc8a13f615">ARM_MCI_CONTROL_CLOCK_IDLE</a>   (0x07)</td></tr>
<tr class="memdesc:ga889473fbfbdcb89aab4d53cc8a13f615"><td class="mdescLeft"> </td><td class="mdescRight">Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled. <a href="group__mci__mode__ctrls.html#ga889473fbfbdcb89aab4d53cc8a13f615">More...</a><br/></td></tr>
<tr class="separator:ga889473fbfbdcb89aab4d53cc8a13f615"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga98853f60bdc085aeeccd66f7bdf22d3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga98853f60bdc085aeeccd66f7bdf22d3d">ARM_MCI_UHS_TUNING_OPERATION</a>   (0x08)</td></tr>
<tr class="memdesc:ga98853f60bdc085aeeccd66f7bdf22d3d"><td class="mdescLeft"> </td><td class="mdescRight">Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute. <a href="group__mci__mode__ctrls.html#ga98853f60bdc085aeeccd66f7bdf22d3d">More...</a><br/></td></tr>
<tr class="separator:ga98853f60bdc085aeeccd66f7bdf22d3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd3af448e26da5657c1c5a03330476b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gabd3af448e26da5657c1c5a03330476b7">ARM_MCI_UHS_TUNING_RESULT</a>   (0x09)</td></tr>
<tr class="memdesc:gabd3af448e26da5657c1c5a03330476b7"><td class="mdescLeft"> </td><td class="mdescRight">Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error. <a href="group__mci__mode__ctrls.html#gabd3af448e26da5657c1c5a03330476b7">More...</a><br/></td></tr>
<tr class="separator:gabd3af448e26da5657c1c5a03330476b7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga09a58821e42595f0c2e55f8cc2d32ceb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga09a58821e42595f0c2e55f8cc2d32ceb">ARM_MCI_DATA_TIMEOUT</a>   (0x0A)</td></tr>
<tr class="memdesc:ga09a58821e42595f0c2e55f8cc2d32ceb"><td class="mdescLeft"> </td><td class="mdescRight">Set Data timeout; arg = timeout in bus cycles. <a href="group__mci__mode__ctrls.html#ga09a58821e42595f0c2e55f8cc2d32ceb">More...</a><br/></td></tr>
<tr class="separator:ga09a58821e42595f0c2e55f8cc2d32ceb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae97b1a819a5d326b1f1009b0d6d48b5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gae97b1a819a5d326b1f1009b0d6d48b5a">ARM_MCI_CSS_TIMEOUT</a>   (0x0B)</td></tr>
<tr class="memdesc:gae97b1a819a5d326b1f1009b0d6d48b5a"><td class="mdescLeft"> </td><td class="mdescRight">Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles. <a href="group__mci__mode__ctrls.html#gae97b1a819a5d326b1f1009b0d6d48b5a">More...</a><br/></td></tr>
<tr class="separator:gae97b1a819a5d326b1f1009b0d6d48b5a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga19fd7d3b74ac48ca74a2e138b3ee9963"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga19fd7d3b74ac48ca74a2e138b3ee9963">ARM_MCI_MONITOR_SDIO_INTERRUPT</a>   (0x0C)</td></tr>
<tr class="memdesc:ga19fd7d3b74ac48ca74a2e138b3ee9963"><td class="mdescLeft"> </td><td class="mdescRight">Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled. <a href="group__mci__mode__ctrls.html#ga19fd7d3b74ac48ca74a2e138b3ee9963">More...</a><br/></td></tr>
<tr class="separator:ga19fd7d3b74ac48ca74a2e138b3ee9963"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaa10c5aa7a8108aa59c3734b3eec2e3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gaaa10c5aa7a8108aa59c3734b3eec2e3a">ARM_MCI_CONTROL_READ_WAIT</a>   (0x0D)</td></tr>
<tr class="memdesc:gaaa10c5aa7a8108aa59c3734b3eec2e3a"><td class="mdescLeft"> </td><td class="mdescRight">Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled. <a href="group__mci__mode__ctrls.html#gaaa10c5aa7a8108aa59c3734b3eec2e3a">More...</a><br/></td></tr>
<tr class="separator:gaaa10c5aa7a8108aa59c3734b3eec2e3a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga04cf174b0ef13240f26225bf8e45a4a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga04cf174b0ef13240f26225bf8e45a4a0">ARM_MCI_SUSPEND_TRANSFER</a>   (0x0E)</td></tr>
<tr class="memdesc:ga04cf174b0ef13240f26225bf8e45a4a0"><td class="mdescLeft"> </td><td class="mdescRight">Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer. <a href="group__mci__mode__ctrls.html#ga04cf174b0ef13240f26225bf8e45a4a0">More...</a><br/></td></tr>
<tr class="separator:ga04cf174b0ef13240f26225bf8e45a4a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac4907319499072fddf61f2f83b0dd966"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gac4907319499072fddf61f2f83b0dd966">ARM_MCI_RESUME_TRANSFER</a>   (0x0F)</td></tr>
<tr class="memdesc:gac4907319499072fddf61f2f83b0dd966"><td class="mdescLeft"> </td><td class="mdescRight">Resume Data transfer (SD I/O) <a href="group__mci__mode__ctrls.html#gac4907319499072fddf61f2f83b0dd966">More...</a><br/></td></tr>
<tr class="separator:gac4907319499072fddf61f2f83b0dd966"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga601fa8b27ab2e5f6d90c93d54c8f412d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga601fa8b27ab2e5f6d90c93d54c8f412d">ARM_MCI_BUS_DEFAULT_SPEED</a>   (0x00)</td></tr>
<tr class="memdesc:ga601fa8b27ab2e5f6d90c93d54c8f412d"><td class="mdescLeft"> </td><td class="mdescRight">SD/MMC: Default Speed mode up to 25/26MHz. <a href="group__mci__bus__speed__ctrls.html#ga601fa8b27ab2e5f6d90c93d54c8f412d">More...</a><br/></td></tr>
<tr class="separator:ga601fa8b27ab2e5f6d90c93d54c8f412d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaabda746ac7d6b4497358ff655a8ea6be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#gaabda746ac7d6b4497358ff655a8ea6be">ARM_MCI_BUS_HIGH_SPEED</a>   (0x01)</td></tr>
<tr class="memdesc:gaabda746ac7d6b4497358ff655a8ea6be"><td class="mdescLeft"> </td><td class="mdescRight">SD/MMC: High Speed mode up to 50/52MHz. <a href="group__mci__bus__speed__ctrls.html#gaabda746ac7d6b4497358ff655a8ea6be">More...</a><br/></td></tr>
<tr class="separator:gaabda746ac7d6b4497358ff655a8ea6be"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0473c44a7b65044b3c6a8e7012009a4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga0473c44a7b65044b3c6a8e7012009a4a">ARM_MCI_BUS_UHS_SDR12</a>   (0x02)</td></tr>
<tr class="memdesc:ga0473c44a7b65044b3c6a8e7012009a4a"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#ga0473c44a7b65044b3c6a8e7012009a4a">More...</a><br/></td></tr>
<tr class="separator:ga0473c44a7b65044b3c6a8e7012009a4a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae32422631052307b3c4d269b25415907"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#gae32422631052307b3c4d269b25415907">ARM_MCI_BUS_UHS_SDR25</a>   (0x03)</td></tr>
<tr class="memdesc:gae32422631052307b3c4d269b25415907"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#gae32422631052307b3c4d269b25415907">More...</a><br/></td></tr>
<tr class="separator:gae32422631052307b3c4d269b25415907"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9f326c02391d965918ae619b912b81e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga9f326c02391d965918ae619b912b81e7">ARM_MCI_BUS_UHS_SDR50</a>   (0x04)</td></tr>
<tr class="memdesc:ga9f326c02391d965918ae619b912b81e7"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#ga9f326c02391d965918ae619b912b81e7">More...</a><br/></td></tr>
<tr class="separator:ga9f326c02391d965918ae619b912b81e7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad2bab563e7bbb4bcf6bdabe6a13dadf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#gad2bab563e7bbb4bcf6bdabe6a13dadf4">ARM_MCI_BUS_UHS_SDR104</a>   (0x05)</td></tr>
<tr class="memdesc:gad2bab563e7bbb4bcf6bdabe6a13dadf4"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#gad2bab563e7bbb4bcf6bdabe6a13dadf4">More...</a><br/></td></tr>
<tr class="separator:gad2bab563e7bbb4bcf6bdabe6a13dadf4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga04da920a5cac99eab9784527057f1b9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga04da920a5cac99eab9784527057f1b9c">ARM_MCI_BUS_UHS_DDR50</a>   (0x06)</td></tr>
<tr class="memdesc:ga04da920a5cac99eab9784527057f1b9c"><td class="mdescLeft"> </td><td class="mdescRight">SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#ga04da920a5cac99eab9784527057f1b9c">More...</a><br/></td></tr>
<tr class="separator:ga04da920a5cac99eab9784527057f1b9c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaed404312d9bc073e3489779a911c7dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__cmd__line__ctrls.html#gaaed404312d9bc073e3489779a911c7dc">ARM_MCI_BUS_CMD_PUSH_PULL</a>   (0x00)</td></tr>
<tr class="memdesc:gaaed404312d9bc073e3489779a911c7dc"><td class="mdescLeft"> </td><td class="mdescRight">Push-Pull CMD line (default) <a href="group__mci__cmd__line__ctrls.html#gaaed404312d9bc073e3489779a911c7dc">More...</a><br/></td></tr>
<tr class="separator:gaaed404312d9bc073e3489779a911c7dc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaadf8667985731964d57d1ed672e90fd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__cmd__line__ctrls.html#gaadf8667985731964d57d1ed672e90fd3">ARM_MCI_BUS_CMD_OPEN_DRAIN</a>   (0x01)</td></tr>
<tr class="memdesc:gaadf8667985731964d57d1ed672e90fd3"><td class="mdescLeft"> </td><td class="mdescRight">Open Drain CMD line (MMC only) <a href="group__mci__cmd__line__ctrls.html#gaadf8667985731964d57d1ed672e90fd3">More...</a><br/></td></tr>
<tr class="separator:gaadf8667985731964d57d1ed672e90fd3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa09a00d810a4dfd1d1824311ee290585"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#gaa09a00d810a4dfd1d1824311ee290585">ARM_MCI_BUS_DATA_WIDTH_1</a>   (0x00)</td></tr>
<tr class="memdesc:gaa09a00d810a4dfd1d1824311ee290585"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 1 bit (default) <a href="group__mci__bus__data__width__ctrls.html#gaa09a00d810a4dfd1d1824311ee290585">More...</a><br/></td></tr>
<tr class="separator:gaa09a00d810a4dfd1d1824311ee290585"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa28150d8c3789e8cf1bcda318f74a28c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#gaa28150d8c3789e8cf1bcda318f74a28c">ARM_MCI_BUS_DATA_WIDTH_4</a>   (0x01)</td></tr>
<tr class="memdesc:gaa28150d8c3789e8cf1bcda318f74a28c"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 4 bits. <a href="group__mci__bus__data__width__ctrls.html#gaa28150d8c3789e8cf1bcda318f74a28c">More...</a><br/></td></tr>
<tr class="separator:gaa28150d8c3789e8cf1bcda318f74a28c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3bb99a2d98ba9fb8c5bc97fa2b8ef469"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#ga3bb99a2d98ba9fb8c5bc97fa2b8ef469">ARM_MCI_BUS_DATA_WIDTH_8</a>   (0x02)</td></tr>
<tr class="memdesc:ga3bb99a2d98ba9fb8c5bc97fa2b8ef469"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 8 bits. <a href="group__mci__bus__data__width__ctrls.html#ga3bb99a2d98ba9fb8c5bc97fa2b8ef469">More...</a><br/></td></tr>
<tr class="separator:ga3bb99a2d98ba9fb8c5bc97fa2b8ef469"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaccb174bd131f8fd8cd9a56439a8ebb60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#gaccb174bd131f8fd8cd9a56439a8ebb60">ARM_MCI_BUS_DATA_WIDTH_4_DDR</a>   (0x03)</td></tr>
<tr class="memdesc:gaccb174bd131f8fd8cd9a56439a8ebb60"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only. <a href="group__mci__bus__data__width__ctrls.html#gaccb174bd131f8fd8cd9a56439a8ebb60">More...</a><br/></td></tr>
<tr class="separator:gaccb174bd131f8fd8cd9a56439a8ebb60"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7b31f81ae703229095fe9efcfbe80b47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#ga7b31f81ae703229095fe9efcfbe80b47">ARM_MCI_BUS_DATA_WIDTH_8_DDR</a>   (0x04)</td></tr>
<tr class="memdesc:ga7b31f81ae703229095fe9efcfbe80b47"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only. <a href="group__mci__bus__data__width__ctrls.html#ga7b31f81ae703229095fe9efcfbe80b47">More...</a><br/></td></tr>
<tr class="separator:ga7b31f81ae703229095fe9efcfbe80b47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga64eb1c4847711a262f084c361b60a912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga64eb1c4847711a262f084c361b60a912">ARM_MCI_DRIVER_TYPE_A</a>   (0x01)</td></tr>
<tr class="memdesc:ga64eb1c4847711a262f084c361b60a912"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type A. <a href="group__mci__driver__strength__ctrls.html#ga64eb1c4847711a262f084c361b60a912">More...</a><br/></td></tr>
<tr class="separator:ga64eb1c4847711a262f084c361b60a912"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga078d3c3bc7c9335b92e6445a0abafc46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga078d3c3bc7c9335b92e6445a0abafc46">ARM_MCI_DRIVER_TYPE_B</a>   (0x00)</td></tr>
<tr class="memdesc:ga078d3c3bc7c9335b92e6445a0abafc46"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type B (default) <a href="group__mci__driver__strength__ctrls.html#ga078d3c3bc7c9335b92e6445a0abafc46">More...</a><br/></td></tr>
<tr class="separator:ga078d3c3bc7c9335b92e6445a0abafc46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3da11696d1fcd3930eb7e70fe097d747"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga3da11696d1fcd3930eb7e70fe097d747">ARM_MCI_DRIVER_TYPE_C</a>   (0x02)</td></tr>
<tr class="memdesc:ga3da11696d1fcd3930eb7e70fe097d747"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type C. <a href="group__mci__driver__strength__ctrls.html#ga3da11696d1fcd3930eb7e70fe097d747">More...</a><br/></td></tr>
<tr class="separator:ga3da11696d1fcd3930eb7e70fe097d747"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8185f82b1d8857a3f0eb461d664f2b3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga8185f82b1d8857a3f0eb461d664f2b3d">ARM_MCI_DRIVER_TYPE_D</a>   (0x03)</td></tr>
<tr class="memdesc:ga8185f82b1d8857a3f0eb461d664f2b3d"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type D. <a href="group__mci__driver__strength__ctrls.html#ga8185f82b1d8857a3f0eb461d664f2b3d">More...</a><br/></td></tr>
<tr class="separator:ga8185f82b1d8857a3f0eb461d664f2b3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8de1e84f879b741ed1e13a0aac93a246"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#a8de1e84f879b741ed1e13a0aac93a246">ARM_MCI_POWER_VDD_Pos</a>   0</td></tr>
<tr class="separator:a8de1e84f879b741ed1e13a0aac93a246"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a58913d82ea4abd60dee50cec024de4a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#a58913d82ea4abd60dee50cec024de4a0">ARM_MCI_POWER_VDD_Msk</a>   (0x0FUL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="separator:a58913d82ea4abd60dee50cec024de4a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga288fbd80b384739a80e8f3ec31205cf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga288fbd80b384739a80e8f3ec31205cf5">ARM_MCI_POWER_VDD_OFF</a>   (0x01UL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="memdesc:ga288fbd80b384739a80e8f3ec31205cf5"><td class="mdescLeft"> </td><td class="mdescRight">VDD (VCC) turned off. <a href="group__mci__card__power__ctrls.html#ga288fbd80b384739a80e8f3ec31205cf5">More...</a><br/></td></tr>
<tr class="separator:ga288fbd80b384739a80e8f3ec31205cf5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga565ecd36c8d0379fb4172da577cc540d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga565ecd36c8d0379fb4172da577cc540d">ARM_MCI_POWER_VDD_3V3</a>   (0x02UL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="memdesc:ga565ecd36c8d0379fb4172da577cc540d"><td class="mdescLeft"> </td><td class="mdescRight">VDD (VCC) = 3.3V. <a href="group__mci__card__power__ctrls.html#ga565ecd36c8d0379fb4172da577cc540d">More...</a><br/></td></tr>
<tr class="separator:ga565ecd36c8d0379fb4172da577cc540d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2ce8e379c3691da3b51c9c97d61770ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga2ce8e379c3691da3b51c9c97d61770ef">ARM_MCI_POWER_VDD_1V8</a>   (0x03UL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="memdesc:ga2ce8e379c3691da3b51c9c97d61770ef"><td class="mdescLeft"> </td><td class="mdescRight">VDD (VCC) = 1.8V. <a href="group__mci__card__power__ctrls.html#ga2ce8e379c3691da3b51c9c97d61770ef">More...</a><br/></td></tr>
<tr class="separator:ga2ce8e379c3691da3b51c9c97d61770ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae2de0ecc2d5d73b134c18b80bedb23a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#ae2de0ecc2d5d73b134c18b80bedb23a7">ARM_MCI_POWER_VCCQ_Pos</a>   4</td></tr>
<tr class="separator:ae2de0ecc2d5d73b134c18b80bedb23a7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aef11db3d5da54f0e0cf2e346f08622e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#aef11db3d5da54f0e0cf2e346f08622e2">ARM_MCI_POWER_VCCQ_Msk</a>   (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="separator:aef11db3d5da54f0e0cf2e346f08622e2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6929c98a6bc8d898939a95111509220b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga6929c98a6bc8d898939a95111509220b">ARM_MCI_POWER_VCCQ_OFF</a>   (0x01UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:ga6929c98a6bc8d898939a95111509220b"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ turned off <a href="group__mci__card__power__ctrls.html#ga6929c98a6bc8d898939a95111509220b">More...</a><br/></td></tr>
<tr class="separator:ga6929c98a6bc8d898939a95111509220b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga91a7201173cc092eaf7f0bcee028871e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga91a7201173cc092eaf7f0bcee028871e">ARM_MCI_POWER_VCCQ_3V3</a>   (0x02UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:ga91a7201173cc092eaf7f0bcee028871e"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ = 3.3V <a href="group__mci__card__power__ctrls.html#ga91a7201173cc092eaf7f0bcee028871e">More...</a><br/></td></tr>
<tr class="separator:ga91a7201173cc092eaf7f0bcee028871e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaf389e0a139d5808dff8ebb6897d4c7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#gaaf389e0a139d5808dff8ebb6897d4c7b">ARM_MCI_POWER_VCCQ_1V8</a>   (0x03UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:gaaf389e0a139d5808dff8ebb6897d4c7b"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ = 1.8V <a href="group__mci__card__power__ctrls.html#gaaf389e0a139d5808dff8ebb6897d4c7b">More...</a><br/></td></tr>
<tr class="separator:gaaf389e0a139d5808dff8ebb6897d4c7b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5304b3b6cadc5113f841c3d526ab5db6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga5304b3b6cadc5113f841c3d526ab5db6">ARM_MCI_POWER_VCCQ_1V2</a>   (0x04UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:ga5304b3b6cadc5113f841c3d526ab5db6"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ = 1.2V <a href="group__mci__card__power__ctrls.html#ga5304b3b6cadc5113f841c3d526ab5db6">More...</a><br/></td></tr>
<tr class="separator:ga5304b3b6cadc5113f841c3d526ab5db6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae2cf8ef238c092e94e96a01602f3a23c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gae2cf8ef238c092e94e96a01602f3a23c">ARM_MCI_EVENT_CARD_INSERTED</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gae2cf8ef238c092e94e96a01602f3a23c"><td class="mdescLeft"> </td><td class="mdescRight">Memory Card inserted. <a href="group__mci__event__gr.html#gae2cf8ef238c092e94e96a01602f3a23c">More...</a><br/></td></tr>
<tr class="separator:gae2cf8ef238c092e94e96a01602f3a23c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga92ba748f9324ec13898f10456f17c8cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga92ba748f9324ec13898f10456f17c8cc">ARM_MCI_EVENT_CARD_REMOVED</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga92ba748f9324ec13898f10456f17c8cc"><td class="mdescLeft"> </td><td class="mdescRight">Memory Card removed. <a href="group__mci__event__gr.html#ga92ba748f9324ec13898f10456f17c8cc">More...</a><br/></td></tr>
<tr class="separator:ga92ba748f9324ec13898f10456f17c8cc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae69356c75d55103d93ef91ac1bc02b49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gae69356c75d55103d93ef91ac1bc02b49">ARM_MCI_EVENT_COMMAND_COMPLETE</a>   (1UL << 2)</td></tr>
<tr class="memdesc:gae69356c75d55103d93ef91ac1bc02b49"><td class="mdescLeft"> </td><td class="mdescRight">Command completed. <a href="group__mci__event__gr.html#gae69356c75d55103d93ef91ac1bc02b49">More...</a><br/></td></tr>
<tr class="separator:gae69356c75d55103d93ef91ac1bc02b49"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab79b3ab4dcd03c38df1e173fa903d822"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gab79b3ab4dcd03c38df1e173fa903d822">ARM_MCI_EVENT_COMMAND_TIMEOUT</a>   (1UL << 3)</td></tr>
<tr class="memdesc:gab79b3ab4dcd03c38df1e173fa903d822"><td class="mdescLeft"> </td><td class="mdescRight">Command timeout. <a href="group__mci__event__gr.html#gab79b3ab4dcd03c38df1e173fa903d822">More...</a><br/></td></tr>
<tr class="separator:gab79b3ab4dcd03c38df1e173fa903d822"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga373aeb3eca0e4c6d159312488a130442"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga373aeb3eca0e4c6d159312488a130442">ARM_MCI_EVENT_COMMAND_ERROR</a>   (1UL << 4)</td></tr>
<tr class="memdesc:ga373aeb3eca0e4c6d159312488a130442"><td class="mdescLeft"> </td><td class="mdescRight">Command response error (CRC error or invalid response) <a href="group__mci__event__gr.html#ga373aeb3eca0e4c6d159312488a130442">More...</a><br/></td></tr>
<tr class="separator:ga373aeb3eca0e4c6d159312488a130442"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc3c468dedaed890683360f2c5c65bea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gabc3c468dedaed890683360f2c5c65bea">ARM_MCI_EVENT_TRANSFER_COMPLETE</a>   (1UL << 5)</td></tr>
<tr class="memdesc:gabc3c468dedaed890683360f2c5c65bea"><td class="mdescLeft"> </td><td class="mdescRight">Data transfer completed. <a href="group__mci__event__gr.html#gabc3c468dedaed890683360f2c5c65bea">More...</a><br/></td></tr>
<tr class="separator:gabc3c468dedaed890683360f2c5c65bea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga614e7c7226adbaa8ec4165bf8b87ef27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga614e7c7226adbaa8ec4165bf8b87ef27">ARM_MCI_EVENT_TRANSFER_TIMEOUT</a>   (1UL << 6)</td></tr>
<tr class="memdesc:ga614e7c7226adbaa8ec4165bf8b87ef27"><td class="mdescLeft"> </td><td class="mdescRight">Data transfer timeout. <a href="group__mci__event__gr.html#ga614e7c7226adbaa8ec4165bf8b87ef27">More...</a><br/></td></tr>
<tr class="separator:ga614e7c7226adbaa8ec4165bf8b87ef27"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5d2cee5ba6d0e40ad505983155706c29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga5d2cee5ba6d0e40ad505983155706c29">ARM_MCI_EVENT_TRANSFER_ERROR</a>   (1UL << 7)</td></tr>
<tr class="memdesc:ga5d2cee5ba6d0e40ad505983155706c29"><td class="mdescLeft"> </td><td class="mdescRight">Data transfer CRC failed. <a href="group__mci__event__gr.html#ga5d2cee5ba6d0e40ad505983155706c29">More...</a><br/></td></tr>
<tr class="separator:ga5d2cee5ba6d0e40ad505983155706c29"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga75a050fdfe04e6816e96c938d6a6c197"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga75a050fdfe04e6816e96c938d6a6c197">ARM_MCI_EVENT_SDIO_INTERRUPT</a>   (1UL << 8)</td></tr>
<tr class="memdesc:ga75a050fdfe04e6816e96c938d6a6c197"><td class="mdescLeft"> </td><td class="mdescRight">SD I/O Interrupt. <a href="group__mci__event__gr.html#ga75a050fdfe04e6816e96c938d6a6c197">More...</a><br/></td></tr>
<tr class="separator:ga75a050fdfe04e6816e96c938d6a6c197"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8161f3960ddf2a3cdc3c4c83148c6099"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga8161f3960ddf2a3cdc3c4c83148c6099">ARM_MCI_EVENT_CCS</a>   (1UL << 9)</td></tr>
<tr class="memdesc:ga8161f3960ddf2a3cdc3c4c83148c6099"><td class="mdescLeft"> </td><td class="mdescRight">Command Completion Signal (CCS) <a href="group__mci__event__gr.html#ga8161f3960ddf2a3cdc3c4c83148c6099">More...</a><br/></td></tr>
<tr class="separator:ga8161f3960ddf2a3cdc3c4c83148c6099"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafa8cbcd597a05c64901eeb777cc0b74f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gafa8cbcd597a05c64901eeb777cc0b74f">ARM_MCI_EVENT_CCS_TIMEOUT</a>   (1UL << 10)</td></tr>
<tr class="memdesc:gafa8cbcd597a05c64901eeb777cc0b74f"><td class="mdescLeft"> </td><td class="mdescRight">Command Completion Signal (CCS) Timeout. <a href="group__mci__event__gr.html#gafa8cbcd597a05c64901eeb777cc0b74f">More...</a><br/></td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:ga0d14651f6788c1ffd81544602565faf1"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga0d14651f6788c1ffd81544602565faf1">ARM_MCI_SignalEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:ga0d14651f6788c1ffd81544602565faf1"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__mci__interface__gr.html#gaac2dbd1c1a98436938c5d0d6248cb700">ARM_MCI_SignalEvent</a> : Signal MCI Card Event. <a href="group__mci__interface__gr.html#ga0d14651f6788c1ffd81544602565faf1">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ARM_MCI_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td>
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<td class="memname">#define ARM_MCI_RESPONSE_Pos   0</td>
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<td class="memname">#define ARM_MCI_RESPONSE_Msk   (3UL << ARM_MCI_RESPONSE_Pos)</td>
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<td class="memname">#define ARM_MCI_POWER_VDD_Pos   0</td>
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<td class="memname">#define ARM_MCI_POWER_VDD_Msk   (0x0FUL << ARM_MCI_POWER_VDD_Pos)</td>
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<td class="memname">#define ARM_MCI_POWER_VCCQ_Pos   4</td>
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<td class="memname">#define ARM_MCI_POWER_VCCQ_Msk   (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)</td>
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