diff options
| author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
|---|---|---|
| committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
| commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
| tree | 8a6e0dda832555c692307869aed49d07ee7facfe /docs/RTOS2/html/pHardwareRequirements.html | |
| parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
| download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip | |
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder.
Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
used in existing projects, and thus avoid projects mass update
Note: the following components have been removed from ARM original delivery (as not used in ST packages)
- CMSIS_EW2018.pdf
- .gitattributes
- .gitignore
- \Device
- \CMSIS
- \CoreValidation
- \DAP
- \Documentation
- \DoxyGen
- \Driver
- \Pack
- \RTOS\CMSIS_RTOS_Tutorial.pdf
- \RTOS\RTX
- \RTOS\Template
- \RTOS2\RTX
- \Utilities
- All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2
Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/RTOS2/html/pHardwareRequirements.html')
| -rw-r--r-- | docs/RTOS2/html/pHardwareRequirements.html | 221 |
1 files changed, 221 insertions, 0 deletions
diff --git a/docs/RTOS2/html/pHardwareRequirements.html b/docs/RTOS2/html/pHardwareRequirements.html new file mode 100644 index 0000000..fac09bb --- /dev/null +++ b/docs/RTOS2/html/pHardwareRequirements.html @@ -0,0 +1,221 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Hardware Requirements</title> +<title>CMSIS-RTOS2: Hardware Requirements</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-RTOS2 +  <span id="projectnumber">Version 2.1.3</span> + </div> + <div id="projectbrief">Real-Time Operating System: API and RTX Reference Implementation</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('pHardwareRequirements.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Macros</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(9)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(10)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Hardware Requirements </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>The following section lists the hardware requirements for RTX v5 on the various supported target processors:</p> +<h1><a class="anchor" id="tpProcessor"></a> +Processor Requirements</h1> +<p>RTX assumes a fully function-able processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.</p> +<h2><a class="anchor" id="tpCortexM0_M0P_M23"></a> +Cortex-M0/M0+/M23 target processor</h2> +<table class="doxtable"> +<tr> +<th align="left">Hardware Requirement </th><th align="left">Description </th></tr> +<tr> +<td align="left">SysTick timer </td><td align="left">The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> </td></tr> +<tr> +<td align="left">Exception Handler </td><td align="left">RTX implements exception handlers for SVC, PendSV, and SysTick interrupt </td></tr> +<tr> +<td align="left">Core Registers </td><td align="left">The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK </td></tr> +<tr> +<td align="left">System Control Block (SBC) </td><td align="left">To control and setup the processor exceptions including PendSV and SVC </td></tr> +<tr> +<td align="left">Interrupt Control </td><td align="left">The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register. </td></tr> +</table> +<p>The interface files to the processor hardware are:</p> +<ul> +<li><b>irq_cm0.s</b> defines exception handlers for Cortex-M0/M0+</li> +<li><b>irq_armv8mbl_common.s</b> defines exception handlers for Cortex-M23</li> +<li><b>rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.</li> +<li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the SysTick timer.</li> +</ul> +<dl class="section note"><dt>Note</dt><dd><ul> +<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used to configure the SysTick timer.</li> +</ul> +</dd></dl> +<h2><a class="anchor" id="tpCortexM3_M4_M7_M33"></a> +Cortex-M3/M4/M7/M33 target processor</h2> +<table class="doxtable"> +<tr> +<th align="left">Hardware Requirement </th><th align="left">Description </th></tr> +<tr> +<td align="left">SysTick timer </td><td align="left">The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> </td></tr> +<tr> +<td align="left">Exception Handler </td><td align="left">RTX implements exception handlers for SVC, PendSV, and SysTick interrupt </td></tr> +<tr> +<td align="left">Core Registers </td><td align="left">The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK, BASEPRI </td></tr> +<tr> +<td align="left">System Control Block (SBC) </td><td align="left">To control and setup the processor exceptions including PendSV and SVC </td></tr> +<tr> +<td align="left">NVIC Interface </td><td align="left">The CMSIS-Core function NVIC_GetPriorityGrouping to setup interrupt priorities. </td></tr> +<tr> +<td align="left">LDREX, STREX instruction </td><td align="left">Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions. </td></tr> +</table> +<p>The interface files to the processor hardware are:</p> +<ul> +<li><b>irq_cm3.s</b> defines exception handlers for Cortex-M3 and Cortex-M4/M7 without floating point unit.</li> +<li><b>irq_cm4f.s</b> defines exception handlers for Cortex-M4/M7 with floating point unit.</li> +<li><b>irq_armv8mml_common.s</b> defines exception handlers for Cortex-M33</li> +<li><b>rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.</li> +<li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the SysTick timer.</li> +</ul> +<dl class="section note"><dt>Note</dt><dd><ul> +<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used to configure the SysTick timer.</li> +</ul> +</dd></dl> +<h2><a class="anchor" id="tpCortexA5_A7_A9"></a> +Cortex-A5/A7/A9 target processor</h2> +<table class="doxtable"> +<tr> +<th align="left">Hardware Requirement </th><th align="left">Description </th></tr> +<tr> +<td align="left">Timer Peripheral </td><td align="left">An arbitrary timer peripheral generates the kernel tick interrupts. The interfaces for Cortex-A Generic Timer and Private Timer are implemented in os_tick_gtim.c and os_tick_ptim.c using the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> </td></tr> +<tr> +<td align="left">Exception Handler </td><td align="left">RTX implements exception handlers for SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction interrupt. </td></tr> +<tr> +<td align="left">Core Registers </td><td align="left">The processor status is read using the following core registers: CPSR, CPACR and FPSCR. </td></tr> +<tr> +<td align="left">LDREX, STREX instruction </td><td align="left">Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions. </td></tr> +<tr> +<td align="left">Interrupt Controller </td><td align="left">An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in irq_ctrl_gic.c using the <a href="../../Core_A/html/group__irq__ctrl__gr.html" class="el">IRQ Controller API</a>. </td></tr> +</table> +<p>The interface files to the processor hardware are:</p> +<ul> +<li><b>irq_ca.s</b> defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.</li> +<li><b>rtx_core_ca.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.</li> +<li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the timer peripheral.</li> +<li><b>irq_ctrl.h</b> is the <a href="../../Core_A/html/group__irq__ctrl__gr.html" class="el">IRQ Controller API</a> that defines the interface functions to the interrupt controller.</li> +</ul> +<dl class="section note"><dt>Note</dt><dd><ul> +<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used to configure the timer peripheral.</li> +</ul> +</dd></dl> +<h1><a class="anchor" id="rMemory"></a> +Memory Requirements</h1> +<p>RTX requires RAM memory that is accessible with contiguous linear addressing. When memory is split across multiple memory banks, some systems do not accept multiple load or store operations on this memory blocks.</p> +<p>RTX does not implement any confidence test for memory validation. This should be implemented by an user-supplied software test library. </p> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="index.html">index</a></li><li class="navelem"><a class="el" href="rtx5_impl.html">RTX v5 Implementation</a></li><li class="navelem"><a class="el" href="technicalData5.html">Technical Data</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:45 for CMSIS-RTOS2 by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |