From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/RTOS2/html/pHardwareRequirements.html | 221 +++++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) create mode 100644 docs/RTOS2/html/pHardwareRequirements.html (limited to 'docs/RTOS2/html/pHardwareRequirements.html') diff --git a/docs/RTOS2/html/pHardwareRequirements.html b/docs/RTOS2/html/pHardwareRequirements.html new file mode 100644 index 0000000..fac09bb --- /dev/null +++ b/docs/RTOS2/html/pHardwareRequirements.html @@ -0,0 +1,221 @@ + + + + + +Hardware Requirements +CMSIS-RTOS2: Hardware Requirements + + + + + + + + + + + + + + +
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CMSIS-RTOS2 +  Version 2.1.3 +
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Real-Time Operating System: API and RTX Reference Implementation
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Hardware Requirements
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The following section lists the hardware requirements for RTX v5 on the various supported target processors:

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+Processor Requirements

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RTX assumes a fully function-able processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.

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+Cortex-M0/M0+/M23 target processor

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Hardware Requirement Description
SysTick timer The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the OS Tick API
Exception Handler RTX implements exception handlers for SVC, PendSV, and SysTick interrupt
Core Registers The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK
System Control Block (SBC) To control and setup the processor exceptions including PendSV and SVC
Interrupt Control The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register.
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The interface files to the processor hardware are:

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  • irq_cm0.s defines exception handlers for Cortex-M0/M0+
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  • irq_armv8mbl_common.s defines exception handlers for Cortex-M23
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  • rtx_core_cm.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
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  • os_tick.h is the OS Tick API that defines the interface functions to the SysTick timer.
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Note
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  • The CMSIS-Core variable SystemCoreClock is used to configure the SysTick timer.
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+Cortex-M3/M4/M7/M33 target processor

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Hardware Requirement Description
SysTick timer The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the OS Tick API
Exception Handler RTX implements exception handlers for SVC, PendSV, and SysTick interrupt
Core Registers The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK, BASEPRI
System Control Block (SBC) To control and setup the processor exceptions including PendSV and SVC
NVIC Interface The CMSIS-Core function NVIC_GetPriorityGrouping to setup interrupt priorities.
LDREX, STREX instruction Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions.
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The interface files to the processor hardware are:

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  • irq_cm3.s defines exception handlers for Cortex-M3 and Cortex-M4/M7 without floating point unit.
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  • irq_cm4f.s defines exception handlers for Cortex-M4/M7 with floating point unit.
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  • irq_armv8mml_common.s defines exception handlers for Cortex-M33
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  • rtx_core_cm.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
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  • os_tick.h is the OS Tick API that defines the interface functions to the SysTick timer.
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Note
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  • The CMSIS-Core variable SystemCoreClock is used to configure the SysTick timer.
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+Cortex-A5/A7/A9 target processor

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Hardware Requirement Description
Timer Peripheral An arbitrary timer peripheral generates the kernel tick interrupts. The interfaces for Cortex-A Generic Timer and Private Timer are implemented in os_tick_gtim.c and os_tick_ptim.c using the OS Tick API
Exception Handler RTX implements exception handlers for SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction interrupt.
Core Registers The processor status is read using the following core registers: CPSR, CPACR and FPSCR.
LDREX, STREX instruction Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions.
Interrupt Controller An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in irq_ctrl_gic.c using the IRQ Controller API.
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The interface files to the processor hardware are:

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  • irq_ca.s defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.
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  • rtx_core_ca.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
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  • os_tick.h is the OS Tick API that defines the interface functions to the timer peripheral.
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  • irq_ctrl.h is the IRQ Controller API that defines the interface functions to the interrupt controller.
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  • The CMSIS-Core variable SystemCoreClock is used to configure the timer peripheral.
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+Memory Requirements

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RTX requires RAM memory that is accessible with contiguous linear addressing. When memory is split across multiple memory banks, some systems do not accept multiple load or store operations on this memory blocks.

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RTX does not implement any confidence test for memory validation. This should be implemented by an user-supplied software test library.

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