summaryrefslogtreecommitdiff
path: root/docs/Driver/html/group__spi__interface__gr.js
diff options
context:
space:
mode:
authorAli Labbene <ali.labbene@st.com>2019-12-11 08:59:21 +0100
committerAli Labbene <ali.labbene@st.com>2019-12-16 16:35:24 +0100
commit9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch)
tree8a6e0dda832555c692307869aed49d07ee7facfe /docs/Driver/html/group__spi__interface__gr.js
parent76177aa280494bb36d7a0bcbda1078d4db717020 (diff)
downloadst-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz
st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2
st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/Driver/html/group__spi__interface__gr.js')
-rw-r--r--docs/Driver/html/group__spi__interface__gr.js45
1 files changed, 45 insertions, 0 deletions
diff --git a/docs/Driver/html/group__spi__interface__gr.js b/docs/Driver/html/group__spi__interface__gr.js
new file mode 100644
index 0000000..3af0e0e
--- /dev/null
+++ b/docs/Driver/html/group__spi__interface__gr.js
@@ -0,0 +1,45 @@
+var group__spi__interface__gr =
+[
+ [ "Status Error Codes", "group__spi__execution__status.html", "group__spi__execution__status" ],
+ [ "SPI Events", "group__SPI__events.html", "group__SPI__events" ],
+ [ "SPI Control Codes", "group__SPI__control.html", "group__SPI__control" ],
+ [ "ARM_DRIVER_SPI", "group__spi__interface__gr.html#structARM__DRIVER__SPI", [
+ [ "GetVersion", "group__spi__interface__gr.html#a8834b281da48583845c044a81566c1b3", null ],
+ [ "GetCapabilities", "group__spi__interface__gr.html#a065b5fc24d0204692f0f95a44351ac1e", null ],
+ [ "Initialize", "group__spi__interface__gr.html#afac50d0b28860f7b569293e6b713f8a4", null ],
+ [ "Uninitialize", "group__spi__interface__gr.html#adcf20681a1402869ecb5c6447fada17b", null ],
+ [ "PowerControl", "group__spi__interface__gr.html#aba8f1c8019af95ffe19c32403e3240ef", null ],
+ [ "Send", "group__spi__interface__gr.html#a44eedddf4428cf4b98883b6c27d31922", null ],
+ [ "Receive", "group__spi__interface__gr.html#adb9224a35fe16c92eb0dd103638e4cf3", null ],
+ [ "Transfer", "group__spi__interface__gr.html#ad88b63ed74c03ba06b0599ab06ad4cf7", null ],
+ [ "GetDataCount", "group__spi__interface__gr.html#ad1d892ab3932f65cd7cdf2d0a91ae5da", null ],
+ [ "Control", "group__spi__interface__gr.html#a6e0f47a92f626a971c5197fca6545505", null ],
+ [ "GetStatus", "group__spi__interface__gr.html#a7305e7248420cdb4b02ceba87672178d", null ]
+ ] ],
+ [ "ARM_SPI_CAPABILITIES", "group__spi__interface__gr.html#structARM__SPI__CAPABILITIES", [
+ [ "simplex", "group__spi__interface__gr.html#af244e2c2facf6414e3886495ee6b40bc", null ],
+ [ "ti_ssi", "group__spi__interface__gr.html#a8053c540e5d531b692224bdc2463f36a", null ],
+ [ "microwire", "group__spi__interface__gr.html#a9b4e858eb1d414128994742bf121f94c", null ],
+ [ "event_mode_fault", "group__spi__interface__gr.html#a309619714f0c4febaa497ebdb9b7e3ca", null ],
+ [ "reserved", "group__spi__interface__gr.html#aa43c4c21b173ada1b6b7568956f0d650", null ]
+ ] ],
+ [ "ARM_SPI_STATUS", "group__spi__interface__gr.html#structARM__SPI__STATUS", [
+ [ "busy", "group__spi__interface__gr.html#a50c88f3c1d787773e2ac1b59533f034a", null ],
+ [ "data_lost", "group__spi__interface__gr.html#a9675630df67587ecd171c7ef12b9d22a", null ],
+ [ "mode_fault", "group__spi__interface__gr.html#aeaf54ec655b7a64b9e88578c5f39d4e3", null ],
+ [ "reserved", "group__spi__interface__gr.html#aa43c4c21b173ada1b6b7568956f0d650", null ]
+ ] ],
+ [ "ARM_SPI_SignalEvent_t", "group__spi__interface__gr.html#gafde9205364241ee81290adc0481c6640", null ],
+ [ "ARM_SPI_GetVersion", "group__spi__interface__gr.html#gad5db9209ef1d64a7915a7278d6a402c8", null ],
+ [ "ARM_SPI_GetCapabilities", "group__spi__interface__gr.html#gaf4823a11ab5efcd47c79b13801513ddc", null ],
+ [ "ARM_SPI_Initialize", "group__spi__interface__gr.html#ga1a3c11ed523a4355cd91069527945906", null ],
+ [ "ARM_SPI_Uninitialize", "group__spi__interface__gr.html#ga0c480ee3eabb82fc746e89741ed2e03e", null ],
+ [ "ARM_SPI_PowerControl", "group__spi__interface__gr.html#ga1a1e7e80ea32ae381b75213c32aa8067", null ],
+ [ "ARM_SPI_Send", "group__spi__interface__gr.html#gab2a303d1071e926280d50682f4808479", null ],
+ [ "ARM_SPI_Receive", "group__spi__interface__gr.html#ga726aff54e782ed9b47f7ba1280a3d8f6", null ],
+ [ "ARM_SPI_Transfer", "group__spi__interface__gr.html#gaa24026b3822c10272e301f1505136ec2", null ],
+ [ "ARM_SPI_GetDataCount", "group__spi__interface__gr.html#gaaaecaaf4ec1922f22e7f9de63af5ccdb", null ],
+ [ "ARM_SPI_Control", "group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a", null ],
+ [ "ARM_SPI_GetStatus", "group__spi__interface__gr.html#ga60d33d8788a76c388cc36e066240b817", null ],
+ [ "ARM_SPI_SignalEvent", "group__spi__interface__gr.html#ga505b2d787348d51351d38fee98ccba7e", null ]
+]; \ No newline at end of file