summaryrefslogtreecommitdiff
path: root/docs/DSP/html/search/variables_f.js
diff options
context:
space:
mode:
authorAli Labbene <ali.labbene@st.com>2019-12-11 08:59:21 +0100
committerAli Labbene <ali.labbene@st.com>2019-12-16 16:35:24 +0100
commit9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch)
tree8a6e0dda832555c692307869aed49d07ee7facfe /docs/DSP/html/search/variables_f.js
parent76177aa280494bb36d7a0bcbda1078d4db717020 (diff)
downloadst-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz
st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2
st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/DSP/html/search/variables_f.js')
-rw-r--r--docs/DSP/html/search/variables_f.js21
1 files changed, 21 insertions, 0 deletions
diff --git a/docs/DSP/html/search/variables_f.js b/docs/DSP/html/search/variables_f.js
new file mode 100644
index 0000000..3508269
--- /dev/null
+++ b/docs/DSP/html/search/variables_f.js
@@ -0,0 +1,21 @@
+var searchData=
+[
+ ['sinoutput',['sinOutput',['../arm__sin__cos__example__f32_8c.html#a1e232694019f6b61710fbff5ee27126c',1,'arm_sin_cos_example_f32.c']]],
+ ['sinsquareoutput',['sinSquareOutput',['../arm__sin__cos__example__f32_8c.html#aa5a66e866ebb91eb971f2805209e9d36',1,'arm_sin_cos_example_f32.c']]],
+ ['sint',['Sint',['../structarm__rfft__fast__instance__f32.html#a37419ababdfb3151b1891ae6bcd21012',1,'arm_rfft_fast_instance_f32']]],
+ ['sintable_5ff32',['sinTable_f32',['../arm__common__tables_8h.html#a1dec82d596780f1a66ef4f76f137c1d9',1,'sinTable_f32():&#160;arm_common_tables.c'],['../arm__common__tables_8c.html#a1dec82d596780f1a66ef4f76f137c1d9',1,'sinTable_f32():&#160;arm_common_tables.c']]],
+ ['sintable_5fq15',['sinTable_q15',['../arm__common__tables_8h.html#a9cbcfe313f61add745ebfeddb4fecd55',1,'sinTable_q15():&#160;arm_common_tables.c'],['../arm__common__tables_8c.html#a9cbcfe313f61add745ebfeddb4fecd55',1,'sinTable_q15():&#160;arm_common_tables.c']]],
+ ['sintable_5fq31',['sinTable_q31',['../arm__common__tables_8h.html#a8bfccee9e1c0042cf4a765f4b19d097d',1,'sinTable_q31():&#160;arm_common_tables.c'],['../arm__common__tables_8c.html#a8bfccee9e1c0042cf4a765f4b19d097d',1,'sinTable_q31():&#160;arm_common_tables.c']]],
+ ['snr',['snr',['../arm__convolution__example__f32_8c.html#af06013f588a7003278de222913c9d819',1,'snr():&#160;arm_convolution_example_f32.c'],['../arm__fir__example__f32_8c.html#af06013f588a7003278de222913c9d819',1,'snr():&#160;arm_fir_example_f32.c'],['../arm__graphic__equalizer__example__q31_8c.html#af06013f588a7003278de222913c9d819',1,'snr():&#160;arm_graphic_equalizer_example_q31.c'],['../arm__matrix__example__f32_8c.html#af06013f588a7003278de222913c9d819',1,'snr():&#160;arm_matrix_example_f32.c']]],
+ ['snr1',['snr1',['../arm__linear__interp__example__f32_8c.html#ad492c21cf2dd4e9199ae46c77f812cbc',1,'arm_linear_interp_example_f32.c']]],
+ ['snr2',['snr2',['../arm__linear__interp__example__f32_8c.html#a269948ab25f230d33e3f22eab85aa1cf',1,'arm_linear_interp_example_f32.c']]],
+ ['srca_5fbuf_5ff32',['srcA_buf_f32',['../arm__dotproduct__example__f32_8c.html#a0c248a472fdc0507e4ab7d693e4876b6',1,'arm_dotproduct_example_f32.c']]],
+ ['srcalen',['srcALen',['../arm__convolution__example__f32_8c.html#ace48ed566e2cd6a680f0681192e6af28',1,'arm_convolution_example_f32.c']]],
+ ['srcb_5fbuf_5ff32',['srcB_buf_f32',['../arm__dotproduct__example__f32_8c.html#a67d9082c1585d4854ae9ca38db170ff5',1,'arm_dotproduct_example_f32.c']]],
+ ['srcblen',['srcBLen',['../arm__convolution__example__f32_8c.html#aea71286f498978c5ed3775609b974fc8',1,'arm_convolution_example_f32.c']]],
+ ['state',['state',['../structarm__pid__instance__q15.html#a4a3f0a878b5b6b055e3478a2f244cd30',1,'arm_pid_instance_q15::state()'],['../structarm__pid__instance__q31.html#a228e4a64da6014844a0a671a1fa391d4',1,'arm_pid_instance_q31::state()'],['../structarm__pid__instance__f32.html#afd394e1e52fb1d526aa472c83b8f2464',1,'arm_pid_instance_f32::state()']]],
+ ['stateindex',['stateIndex',['../structarm__fir__sparse__instance__f32.html#a57585aeca9dc8686e08df2865375a86d',1,'arm_fir_sparse_instance_f32::stateIndex()'],['../structarm__fir__sparse__instance__q31.html#a557ed9d477e76e4ad2019344f19f568a',1,'arm_fir_sparse_instance_q31::stateIndex()'],['../structarm__fir__sparse__instance__q15.html#a89487f28cab52637426024005e478985',1,'arm_fir_sparse_instance_q15::stateIndex()'],['../structarm__fir__sparse__instance__q7.html#a2d2e65473fe3a3f2b953b4e0b60824df',1,'arm_fir_sparse_instance_q7::stateIndex()']]],
+ ['status',['status',['../arm__dotproduct__example__f32_8c.html#a88ccb294236ab22b00310c47164c53c3',1,'status():&#160;arm_dotproduct_example_f32.c'],['../arm__sin__cos__example__f32_8c.html#a88ccb294236ab22b00310c47164c53c3',1,'status():&#160;arm_sin_cos_example_f32.c']]],
+ ['std',['std',['../arm__class__marks__example__f32_8c.html#a150b0cf729b51893379f5b5548d4f989',1,'arm_class_marks_example_f32.c']]],
+ ['student_5fnum',['student_num',['../arm__class__marks__example__f32_8c.html#a798cf43a3725d7df2fcaf3f328969f53',1,'arm_class_marks_example_f32.c']]]
+];