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| author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
|---|---|---|
| committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
| commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
| tree | 8a6e0dda832555c692307869aed49d07ee7facfe /docs/Core_A/html/structTimer__Type.html | |
| parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
| download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip | |
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder.
Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
used in existing projects, and thus avoid projects mass update
Note: the following components have been removed from ARM original delivery (as not used in ST packages)
- CMSIS_EW2018.pdf
- .gitattributes
- .gitignore
- \Device
- \CMSIS
- \CoreValidation
- \DAP
- \Documentation
- \DoxyGen
- \Driver
- \Pack
- \RTOS\CMSIS_RTOS_Tutorial.pdf
- \RTOS\RTX
- \RTOS\Template
- \RTOS2\RTX
- \Utilities
- All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2
Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/Core_A/html/structTimer__Type.html')
| -rw-r--r-- | docs/Core_A/html/structTimer__Type.html | 368 |
1 files changed, 368 insertions, 0 deletions
diff --git a/docs/Core_A/html/structTimer__Type.html b/docs/Core_A/html/structTimer__Type.html new file mode 100644 index 0000000..54e1a7e --- /dev/null +++ b/docs/Core_A/html/structTimer__Type.html @@ -0,0 +1,368 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Timer_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-A): Timer_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> 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+<div class="title">Timer_Type Struct Reference<div class="ingroups"><a class="el" href="group__PTM__timer__functions.html">Private Timer Functions</a></div></div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the Private Timer. +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a073457d2d18c2eff93fd12aec81ef20b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a073457d2d18c2eff93fd12aec81ef20b">LOAD</a></td></tr> +<tr class="memdesc:a073457d2d18c2eff93fd12aec81ef20b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Private Timer Load Register. <a href="#a073457d2d18c2eff93fd12aec81ef20b">More...</a><br/></td></tr> +<tr class="separator:a073457d2d18c2eff93fd12aec81ef20b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac933977724591e6ca87d91848fc7a6b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#ac933977724591e6ca87d91848fc7a6b6">COUNTER</a></td></tr> +<tr class="memdesc:ac933977724591e6ca87d91848fc7a6b6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Private Timer Counter Register. <a href="#ac933977724591e6ca87d91848fc7a6b6">More...</a><br/></td></tr> +<tr class="separator:ac933977724591e6ca87d91848fc7a6b6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a91845c88231f4f337be2810d73bc79e4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a91845c88231f4f337be2810d73bc79e4">CONTROL</a></td></tr> +<tr class="memdesc:a91845c88231f4f337be2810d73bc79e4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Private Timer Control Register. <a href="#a91845c88231f4f337be2810d73bc79e4">More...</a><br/></td></tr> +<tr class="separator:a91845c88231f4f337be2810d73bc79e4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ace17db6ca92940b030ad2ccbc674877e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#ace17db6ca92940b030ad2ccbc674877e">ISR</a></td></tr> +<tr class="memdesc:ace17db6ca92940b030ad2ccbc674877e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Private Timer Interrupt Status Register. <a href="#ace17db6ca92940b030ad2ccbc674877e">More...</a><br/></td></tr> +<tr class="separator:ace17db6ca92940b030ad2ccbc674877e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6855bbb5d49f336c9f995dcce492455a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a6855bbb5d49f336c9f995dcce492455a">WLOAD</a></td></tr> +<tr class="memdesc:a6855bbb5d49f336c9f995dcce492455a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/W) Watchdog Load Register. <a href="#a6855bbb5d49f336c9f995dcce492455a">More...</a><br/></td></tr> +<tr class="separator:a6855bbb5d49f336c9f995dcce492455a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7a763d92fbcb506a28a22de548934abc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a7a763d92fbcb506a28a22de548934abc">WCOUNTER</a></td></tr> +<tr class="memdesc:a7a763d92fbcb506a28a22de548934abc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) Watchdog Counter Register. <a href="#a7a763d92fbcb506a28a22de548934abc">More...</a><br/></td></tr> +<tr class="separator:a7a763d92fbcb506a28a22de548934abc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac04581b452702517bfbfa61f9af4c6dd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#ac04581b452702517bfbfa61f9af4c6dd">WCONTROL</a></td></tr> +<tr class="memdesc:ac04581b452702517bfbfa61f9af4c6dd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) Watchdog Control Register. <a href="#ac04581b452702517bfbfa61f9af4c6dd">More...</a><br/></td></tr> +<tr class="separator:ac04581b452702517bfbfa61f9af4c6dd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6239a36319b919b809e00dd26db105fc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a6239a36319b919b809e00dd26db105fc">WISR</a></td></tr> +<tr class="memdesc:a6239a36319b919b809e00dd26db105fc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W) Watchdog Interrupt Status Register. <a href="#a6239a36319b919b809e00dd26db105fc">More...</a><br/></td></tr> +<tr class="separator:a6239a36319b919b809e00dd26db105fc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a775e70c9dbf2b562f9884a9e0dded741"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a775e70c9dbf2b562f9884a9e0dded741">WRESET</a></td></tr> +<tr class="memdesc:a775e70c9dbf2b562f9884a9e0dded741"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W) Watchdog Reset Status Register. <a href="#a775e70c9dbf2b562f9884a9e0dded741">More...</a><br/></td></tr> +<tr class="separator:a775e70c9dbf2b562f9884a9e0dded741"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a9d577164e0a55ecd6c630a9720f153c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a9d577164e0a55ecd6c630a9720f153c3">WDISABLE</a></td></tr> +<tr class="memdesc:a9d577164e0a55ecd6c630a9720f153c3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 ( /W) Watchdog Disable Register. <a href="#a9d577164e0a55ecd6c630a9720f153c3">More...</a><br/></td></tr> +<tr class="separator:a9d577164e0a55ecd6c630a9720f153c3"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a91845c88231f4f337be2810d73bc79e4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::CONTROL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Private Timer Control Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:16] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[15:8] </td><td align="left">Prescaler </td><td align="left">The prescaler modifies the clock period for the decrementing event for the Counter Register. </td></tr> +<tr> +<td align="left">[7:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[2] </td><td align="left">IRQ Enable </td><td align="left">If set, the interrupt is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. </td></tr> +<tr> +<td align="left">[1] </td><td align="left">Auto Reload </td><td align="left">If set, each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">Time Enabled </td><td align="left">If set, Timer is enabled and the counter decrements normally. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="ac933977724591e6ca87d91848fc7a6b6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::COUNTER</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Private Timer Counter Register The Timer Counter Register is a decrementing counter.</p> +<p>The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register.</p> +<p>When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops.</p> +<p>When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register.</p> +<p>Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value. </p> + +</div> +</div> +<a class="anchor" id="ace17db6ca92940b030ad2ccbc674877e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t Timer_Type::ISR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Private Timer Interrupt Status Register</p> +<p>The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. </p> + +</div> +</div> +<a class="anchor" id="a073457d2d18c2eff93fd12aec81ef20b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::LOAD</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Private Timer Load Register The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register. </p> + +</div> +</div> +<a class="anchor" id="ac04581b452702517bfbfa61f9af4c6dd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WCONTROL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Watchdog Control Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:16] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[15:8] </td><td align="left">Prescaler </td><td align="left">The prescaler modifies the clock period for the decrementing event for the Counter Register. </td></tr> +<tr> +<td align="left">[7:4] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[3] </td><td align="left">Watchdog Mode </td><td align="left">0 - Timer mode (default), 1 - Watchdog mode </td></tr> +<tr> +<td align="left">[2] </td><td align="left">IT Enable </td><td align="left">Interrupt enable for timer mode. </td></tr> +<tr> +<td align="left">[1] </td><td align="left">Auto Reload </td><td align="left">0 - Single shot mode, 1 - Continuous timer mode </td></tr> +<tr> +<td align="left">[0] </td><td align="left">Watchdog Enable </td><td align="left">0 - Watchdog counter disabled, 1 - Watchdog timer enabled </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="a7a763d92fbcb506a28a22de548934abc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WCOUNTER</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Watchdog Counter Register</p> +<p>The Watchdog Counter Register is a down counter.</p> +<p>The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its current mode:</p> +<ul> +<li>Timer mode: The watchdog interrupt status event flag is set and the interrupt is set as pending in the Interrupt Distributor.</li> +<li>Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ reset request output pin is asserted. </li> +</ul> + +</div> +</div> +<a class="anchor" id="a9d577164e0a55ecd6c630a9720f153c3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t Timer_Type::WDISABLE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Watchdog Disable Register</p> +<p>Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero. </p> + +</div> +</div> +<a class="anchor" id="a6239a36319b919b809e00dd26db105fc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WISR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Watchdog Interrupt Status Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">Event Flag </td><td align="left">The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="a6855bbb5d49f336c9f995dcce492455a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WLOAD</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Watchdog Load Register</p> +<p>The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register. </p> + +</div> +</div> +<a class="anchor" id="a775e70c9dbf2b562f9884a9e0dded741"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WRESET</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Watchdog Reset Status Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">Reset Flag </td><td align="left">The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode) </td></tr> +</table> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structTimer__Type.html">Timer_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:10 for CMSIS-Core (Cortex-A) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |