From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/structTimer__Type.html | 368 ++++++++++++++++++++++++++++++++ 1 file changed, 368 insertions(+) create mode 100644 docs/Core_A/html/structTimer__Type.html (limited to 'docs/Core_A/html/structTimer__Type.html') diff --git a/docs/Core_A/html/structTimer__Type.html b/docs/Core_A/html/structTimer__Type.html new file mode 100644 index 0000000..54e1a7e --- /dev/null +++ b/docs/Core_A/html/structTimer__Type.html @@ -0,0 +1,368 @@ + + + + + +Timer_Type Struct Reference +CMSIS-Core (Cortex-A): Timer_Type Struct Reference + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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Timer_Type Struct Reference
Private Timer Functions
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Structure type to access the Private Timer. +

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__IOM uint32_t LOAD
 Offset: 0x000 (R/W) Private Timer Load Register. More...
 
__IOM uint32_t COUNTER
 Offset: 0x004 (R/W) Private Timer Counter Register. More...
 
__IOM uint32_t CONTROL
 Offset: 0x008 (R/W) Private Timer Control Register. More...
 
__IOM uint32_t ISR
 Offset: 0x00C (R/W) Private Timer Interrupt Status Register. More...
 
__IOM uint32_t WLOAD
 Offset: 0x020 (R/W) Watchdog Load Register. More...
 
__IOM uint32_t WCOUNTER
 Offset: 0x024 (R/W) Watchdog Counter Register. More...
 
__IOM uint32_t WCONTROL
 Offset: 0x028 (R/W) Watchdog Control Register. More...
 
__IOM uint32_t WISR
 Offset: 0x02C (R/W) Watchdog Interrupt Status Register. More...
 
__IOM uint32_t WRESET
 Offset: 0x030 (R/W) Watchdog Reset Status Register. More...
 
__OM uint32_t WDISABLE
 Offset: 0x034 ( /W) Watchdog Disable Register. More...
 
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Field Documentation

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__IOM uint32_t Timer_Type::CONTROL
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Private Timer Control Register

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Bits Name Function
[31:16] - Reserved.
[15:8] Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register.
[7:3] - Reserved.
[2] IRQ Enable If set, the interrupt is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register.
[1] Auto Reload If set, each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register.
[0] Time Enabled If set, Timer is enabled and the counter decrements normally.
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__IOM uint32_t Timer_Type::COUNTER
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Private Timer Counter Register The Timer Counter Register is a decrementing counter.

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The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register.

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When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops.

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When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register.

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Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value.

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__IM uint32_t Timer_Type::ISR
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Private Timer Interrupt Status Register

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The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1.

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__IOM uint32_t Timer_Type::LOAD
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Private Timer Load Register The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register.

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__IOM uint32_t Timer_Type::WCONTROL
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Watchdog Control Register

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Bits Name Function
[31:16] - Reserved.
[15:8] Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register.
[7:4] - Reserved.
[3] Watchdog Mode 0 - Timer mode (default), 1 - Watchdog mode
[2] IT Enable Interrupt enable for timer mode.
[1] Auto Reload 0 - Single shot mode, 1 - Continuous timer mode
[0] Watchdog Enable 0 - Watchdog counter disabled, 1 - Watchdog timer enabled
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__IOM uint32_t Timer_Type::WCOUNTER
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Watchdog Counter Register

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The Watchdog Counter Register is a down counter.

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The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its current mode:

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  • Timer mode: The watchdog interrupt status event flag is set and the interrupt is set as pending in the Interrupt Distributor.
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  • Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ reset request output pin is asserted.
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__IM uint32_t Timer_Type::WDISABLE
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Watchdog Disable Register

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Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.

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__IOM uint32_t Timer_Type::WISR
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Watchdog Interrupt Status Register

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Bits Name Function
[31:1] - Reserved.
[0] Event Flag The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode.
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__IOM uint32_t Timer_Type::WLOAD
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Watchdog Load Register

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The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register.

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__IOM uint32_t Timer_Type::WRESET
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Watchdog Reset Status Register

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Bits Name Function
[31:1] - Reserved.
[0] Reset Flag The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode)
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