diff options
| author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
|---|---|---|
| committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
| commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
| tree | 8a6e0dda832555c692307869aed49d07ee7facfe /docs/Core/html/partition_h_pg.html | |
| parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
| download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip | |
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder.
Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
used in existing projects, and thus avoid projects mass update
Note: the following components have been removed from ARM original delivery (as not used in ST packages)
- CMSIS_EW2018.pdf
- .gitattributes
- .gitignore
- \Device
- \CMSIS
- \CoreValidation
- \DAP
- \Documentation
- \DoxyGen
- \Driver
- \Pack
- \RTOS\CMSIS_RTOS_Tutorial.pdf
- \RTOS\RTX
- \RTOS\Template
- \RTOS2\RTX
- \Utilities
- All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2
Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/Core/html/partition_h_pg.html')
| -rw-r--r-- | docs/Core/html/partition_h_pg.html | 277 |
1 files changed, 277 insertions, 0 deletions
diff --git a/docs/Core/html/partition_h_pg.html b/docs/Core/html/partition_h_pg.html new file mode 100644 index 0000000..f41a311 --- /dev/null +++ b/docs/Core/html/partition_h_pg.html @@ -0,0 +1,277 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>System Partition Header File partition_<device>.h</title> +<title>CMSIS-Core (Cortex-M): System Partition Header File partition_<device>.h</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('partition_h_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">System Partition Header File partition_<device>.h </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>The <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> contains the initial setup of the TrustZone hardware in an Armv8-M system. The function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> is call from <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> and uses the settings in this file to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS). The following initializations are performed:</p> +<ul> +<li><a class="el" href="partition_h_pg.html#sau_ctrlregister_sec">SAU CTRL register settings</a> provides settings for the SAU CTRL register.</li> +<li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li> +<li><a class="el" href="partition_h_pg.html#sau_sleepexception_sec">Configuration of Sleep and Exception behaviour</a> provides device-specific deepsleep and exception settings.</li> +<li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li> +</ul> +<h1><a class="anchor" id="sau_ctrlregister_sec"></a> +SAU CTRL register settings</h1> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>SAU_INIT_CTRL </td><td>0 .. 1 </td><td>0 </td><td>Initialize SAU CTRL register or not<ul> +<li>0: do not initialize SAU CTRL register</li> +<li>1: initialize SAU CTRL register </li> +</ul> +</td></tr> +<tr> +<td>SAU_INIT_CTRL_ENABLE </td><td>0 .. 1 </td><td>0 </td><td>enable/disable the SAU<ul> +<li>0: disable SAU</li> +<li>1: enable SAU </li> +</ul> +</td></tr> +<tr> +<td>SAU_INIT_CTRL_ALLNS </td><td>0 .. 1 </td><td>0 </td><td>value for SAU_CTRL register bit ALLNS<ul> +<li>0: all Memory is Secure</li> +<li>1: all Memory is Non-Secure </li> +</ul> +</td></tr> +</table> +<h1><a class="anchor" id="sau_regions_sect"></a> +Configuration of the SAU Address Regions</h1> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>SAU_REGIONS_MAX </td><td>0 .. tbd </td><td>8 </td><td>maximum number of SAU regions </td></tr> +<tr> +<td>SAU_INIT_REGION<number> </td><td>0 .. 1 </td><td>0 </td><td>initialize SAU region or not<ul> +<li>0: do not initialize SAU region</li> +<li>1: initialize SAU region </li> +</ul> +</td></tr> +<tr> +<td>SAU_INIT_START<number> </td><td>0x00000000 .. 0xFFFFFFE0<br/> + [in steps of 32] </td><td>0x00000000 </td><td>region start address </td></tr> +<tr> +<td>SAU_INIT_END<number> </td><td>0x00000000 .. 0xFFFFFFE0<br/> + [in steps of 32] </td><td>0x00000000 </td><td>region start address </td></tr> +<tr> +<td>SAU_INIT_NSC<number> </td><td>0 .. 1 </td><td>0 </td><td>SAU region attribute<ul> +<li>0: Non-Secure</li> +<li>1: Secure, Non-Secure callable </li> +</ul> +</td></tr> +</table> +<p>The range of <number> is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each <number>.</p> +<p>The following example shows a set of SAU region macros.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#define SAU_REGIONS_MAX 8 </span><span class="comment">/* Max. number of SAU regions */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION0 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START0 0x00000000 </span><span class="comment">/* start address of SAU region 0 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END0 0x001FFFE0 </span><span class="comment">/* end address of SAU region 0 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC0 1</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION1 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START1 0x00200000 </span><span class="comment">/* start address of SAU region 1 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END1 0x003FFFE0 </span><span class="comment">/* end address of SAU region 1 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC1 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION2 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START2 0x20200000 </span><span class="comment">/* start address of SAU region 2 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END2 0x203FFFE0 </span><span class="comment">/* end address of SAU region 2 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC2 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION3 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START3 0x40000000 </span><span class="comment">/* start address of SAU region 3 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END3 0x40040000 </span><span class="comment">/* end address of SAU region 3 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC3 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION4 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START4 0x00000000 </span><span class="comment">/* start address of SAU region 4 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END4 0x00000000 </span><span class="comment">/* end address of SAU region 4 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC4 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION5 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START5 0x00000000 </span><span class="comment">/* start address of SAU region 5 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END5 0x00000000 </span><span class="comment">/* end address of SAU region 5 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC5 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION6 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START6 0x00000000 </span><span class="comment">/* start address of SAU region 6 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END6 0x00000000 </span><span class="comment">/* end address of SAU region 6 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC6 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION7 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START7 0x00000000 </span><span class="comment">/* start address of SAU region 7 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END7 0x00000000 </span><span class="comment">/* end address of SAU region 7 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor">#define SAU_INIT_NSC7 0</span></div> +</div><!-- fragment --><h1><a class="anchor" id="sau_sleepexception_sec"></a> +Configuration of Sleep and Exception behaviour</h1> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>CSR_INIT_DEEPSLEEPS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_CSR register bit DEEPSLEEPS<ul> +<li>0: Deep Sleep can be enabled by Secure and Non-Secure state</li> +<li>1: Deep Sleep can be enabled by Secure state only </li> +</ul> +</td></tr> +<tr> +<td>AIRCR_INIT_SYSRESETREQS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit SYSRESETREQS<ul> +<li>0: System reset request accessible from Secure and Non-Secure state</li> +<li>1: System reset request accessible from Secure state only </li> +</ul> +</td></tr> +<tr> +<td>AIRCR_INIT_PRIS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit PRIS<ul> +<li>0: Priority of Non-Secure exceptions is Not altered</li> +<li>1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF </li> +</ul> +</td></tr> +<tr> +<td>AIRCR_INIT_BFHFNMINS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit BFHFNMINS<ul> +<li>0: BusFault, HardFault, and NMI target are Secure state</li> +<li>1: BusFault, HardFault, and NMI target are Non-Secure state </li> +</ul> +</td></tr> +</table> +<h1><a class="anchor" id="sau_interrupttarget_sec"></a> +Configuration of Interrupt Target settings</h1> +<p>Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>NVIC_INIT_ITNS<number> </td><td>0x00000000 .. 0xFFFFFFFF<br/> + [each bit represents an interrupt] </td><td>0x00000000 </td><td>Interrupt vector target<ul> +<li>0: Secure state</li> +<li>1: Non-Secure state </li> +</ul> +</td></tr> +</table> +<p>The range of <number> is 0 .. (<number of external interrupts> + 31) / 32.</p> +<p>The following example shows the configuration for a maximum of 64 external interrupts.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS0 0x0000122B</span></div> +<div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS1 0x0000003A</span></div> +</div><!-- fragment --> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |