From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/partition_h_pg.html | 277 +++++++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) create mode 100644 docs/Core/html/partition_h_pg.html (limited to 'docs/Core/html/partition_h_pg.html') diff --git a/docs/Core/html/partition_h_pg.html b/docs/Core/html/partition_h_pg.html new file mode 100644 index 0000000..f41a311 --- /dev/null +++ b/docs/Core/html/partition_h_pg.html @@ -0,0 +1,277 @@ + + + + + +System Partition Header File partition_<device>.h +CMSIS-Core (Cortex-M): System Partition Header File partition_<device>.h + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-M) +  Version 5.1.2 +
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CMSIS-Core support for Cortex-M processor-based devices
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System Partition Header File partition_<device>.h
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The System Partition Header File partition_<device>.h contains the initial setup of the TrustZone hardware in an Armv8-M system. The function TZ_SAU_Setup is call from SystemInit and uses the settings in this file to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS). The following initializations are performed:

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+SAU CTRL register settings

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#define Value Range Default Description
SAU_INIT_CTRL 0 .. 1 0 Initialize SAU CTRL register or not
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  • 0: do not initialize SAU CTRL register
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  • 1: initialize SAU CTRL register
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SAU_INIT_CTRL_ENABLE 0 .. 1 0 enable/disable the SAU
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  • 0: disable SAU
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  • 1: enable SAU
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SAU_INIT_CTRL_ALLNS 0 .. 1 0 value for SAU_CTRL register bit ALLNS
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  • 0: all Memory is Secure
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  • 1: all Memory is Non-Secure
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+Configuration of the SAU Address Regions

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#define Value Range Default Description
SAU_REGIONS_MAX 0 .. tbd 8 maximum number of SAU regions
SAU_INIT_REGION<number> 0 .. 1 0 initialize SAU region or not
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  • 0: do not initialize SAU region
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  • 1: initialize SAU region
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SAU_INIT_START<number> 0x00000000 .. 0xFFFFFFE0
+ [in steps of 32] 		0x00000000 region start address
SAU_INIT_END<number> 0x00000000 .. 0xFFFFFFE0
+ [in steps of 32] 		0x00000000 region start address
SAU_INIT_NSC<number> 0 .. 1 0 SAU region attribute
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  • 0: Non-Secure
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  • 1: Secure, Non-Secure callable
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The range of <number> is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each <number>.

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The following example shows a set of SAU region macros.

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#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
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#define SAU_INIT_REGION0 1
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#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
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#define SAU_INIT_END0 0x001FFFE0 /* end address of SAU region 0 */
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#define SAU_INIT_NSC0 1
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#define SAU_INIT_REGION1 1
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#define SAU_INIT_START1 0x00200000 /* start address of SAU region 1 */
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#define SAU_INIT_END1 0x003FFFE0 /* end address of SAU region 1 */
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#define SAU_INIT_NSC1 0
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#define SAU_INIT_REGION2 1
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#define SAU_INIT_START2 0x20200000 /* start address of SAU region 2 */
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#define SAU_INIT_END2 0x203FFFE0 /* end address of SAU region 2 */
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#define SAU_INIT_NSC2 0
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#define SAU_INIT_REGION3 1
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#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
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#define SAU_INIT_END3 0x40040000 /* end address of SAU region 3 */
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#define SAU_INIT_NSC3 0
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#define SAU_INIT_REGION4 0
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#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
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#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
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#define SAU_INIT_NSC4 0
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#define SAU_INIT_REGION5 0
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#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */
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#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */
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#define SAU_INIT_NSC5 0
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#define SAU_INIT_REGION6 0
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#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
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#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
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#define SAU_INIT_NSC6 0
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#define SAU_INIT_REGION7 0
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#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
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#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
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#define SAU_INIT_NSC7 0
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+Configuration of Sleep and Exception behaviour

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#define Value Range Default Description
CSR_INIT_DEEPSLEEPS 0 .. 1 0 value for SCB_CSR register bit DEEPSLEEPS
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  • 0: Deep Sleep can be enabled by Secure and Non-Secure state
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  • 1: Deep Sleep can be enabled by Secure state only
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AIRCR_INIT_SYSRESETREQS 0 .. 1 0 value for SCB_AIRCR register bit SYSRESETREQS
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  • 0: System reset request accessible from Secure and Non-Secure state
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  • 1: System reset request accessible from Secure state only
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AIRCR_INIT_PRIS 0 .. 1 0 value for SCB_AIRCR register bit PRIS
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  • 0: Priority of Non-Secure exceptions is Not altered
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  • 1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF
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AIRCR_INIT_BFHFNMINS 0 .. 1 0 value for SCB_AIRCR register bit BFHFNMINS
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  • 0: BusFault, HardFault, and NMI target are Secure state
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  • 1: BusFault, HardFault, and NMI target are Non-Secure state
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+Configuration of Interrupt Target settings

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Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to Programmers Model with TrustZone for more information.

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#define Value Range Default Description
NVIC_INIT_ITNS<number> 0x00000000 .. 0xFFFFFFFF
+ [each bit represents an interrupt] 		0x00000000 Interrupt vector target
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  • 0: Secure state
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  • 1: Non-Secure state
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The range of <number> is 0 .. (<number of external interrupts> + 31) / 32.

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The following example shows the configuration for a maximum of 64 external interrupts.

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#define NVIC_INIT_ITNS0 0x0000122B
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#define NVIC_INIT_ITNS1 0x0000003A
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+ + + + -- cgit