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| author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
|---|---|---|
| committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
| commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
| tree | 8a6e0dda832555c692307869aed49d07ee7facfe /docs/Core/html/group__mpu__functions.html | |
| parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
| download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip | |
Official ARM version: v5.4.0
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- CMSIS_EW2018.pdf
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Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/Core/html/group__mpu__functions.html')
| -rw-r--r-- | docs/Core/html/group__mpu__functions.html | 576 |
1 files changed, 576 insertions, 0 deletions
diff --git a/docs/Core/html/group__mpu__functions.html b/docs/Core/html/group__mpu__functions.html new file mode 100644 index 0000000..0803dee --- /dev/null +++ b/docs/Core/html/group__mpu__functions.html @@ -0,0 +1,576 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>MPU Functions for Armv7-M</title> +<title>CMSIS-Core (Cortex-M): MPU Functions for Armv7-M</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> 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+Content</h2></td></tr> +<tr class="memitem:group__mpu__defines"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html">Define values</a></td></tr> +<tr class="memdesc:group__mpu__defines"><td class="mdescLeft"> </td><td class="mdescRight">Define values for MPU region setup. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html">MPU_Type</a></td></tr> +<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure type to access the Memory Protection Unit (MPU). <a href="structMPU__Type.html#details">More...</a><br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a></td></tr> +<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Setup information of a single MPU Region. <a href="structARM__MPU__Region__t.html#details">More...</a><br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:ga3fead12dc24a6d00ad53f55a042486ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(Region, BaseAddress)</td></tr> +<tr class="memdesc:ga3fead12dc24a6d00ad53f55a042486ca"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Base Address Register Value. <a href="#ga3fead12dc24a6d00ad53f55a042486ca">More...</a><br/></td></tr> +<tr class="separator:ga3fead12dc24a6d00ad53f55a042486ca"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)</td></tr> +<tr class="memdesc:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Attribute and Size Register Value. <a href="#ga96b93785c92e2dbcb3a2356c25bf2adc">More...</a><br/></td></tr> +<tr class="separator:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc">ARM_MPU_RASR_EX</a>(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)</td></tr> +<tr class="memdesc:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Attribute and Size Register Value. <a href="#ga332ed5f8969dd4df6b61c6ae32ec36dc">More...</a><br/></td></tr> +<tr class="separator:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a> (uint32_t MPU_CTRL)</td></tr> +<tr class="memdesc:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="mdescLeft"> </td><td class="mdescRight">Enable the memory protection unit (MPU) and. <a href="#ga31406efd492ec9a091a70ffa2d8a42fb">More...</a><br/></td></tr> +<tr class="separator:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7cbc0a4a066ed90e85c8176228235d57"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a> ()</td></tr> +<tr class="separator:ga7cbc0a4a066ed90e85c8176228235d57"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">ARM_MPU_ClrRegion</a> (uint32_t rnr)</td></tr> +<tr class="separator:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga16931f9ad84d7289e8218e169ae6db5d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a> (uint32_t rbar, uint32_t rasr)</td></tr> +<tr class="separator:ga16931f9ad84d7289e8218e169ae6db5d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga042ba1a6a1a58795231459ac0410b809"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a> (uint32_t rnr, uint32_t rbar, uint32_t rasr)</td></tr> +<tr class="separator:ga042ba1a6a1a58795231459ac0410b809"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gafa27b26d5847fa8e465584e376b6078a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a> (MPU_Region_t const *table, uint32_t cnt)</td></tr> +<tr class="separator:gafa27b26d5847fa8e465584e376b6078a"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.</p> +<p>The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.</p> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line"><span class="keywordtype">void</span> main() </div> +<div class="line">{</div> +<div class="line"> <span class="comment">// Set Region 0</span></div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>(0UL, 0x08000000UL, MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));</div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a>(0);</div> +<div class="line"> </div> +<div class="line"> <span class="comment">// Execute application code that is access protected by the MPU</span></div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a>();</div> +<div class="line">}</div> +</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="ga96b93785c92e2dbcb3a2356c25bf2adc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RASR</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">DisableExec, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">AccessPermission, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">TypeExtField, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">IsShareable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">IsCacheable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">IsBufferable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">SubRegionDisable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">Size </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">DisableExec</td><td>Instruction access disable bit. 1 = disable instruction fetches. </td></tr> + <tr><td class="paramname">AccessPermission</td><td>Data access permission configures read/write access for User and Privileged mode. Possible values see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr> + <tr><td class="paramname">TypeExtField</td><td>Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. </td></tr> + <tr><td class="paramname">IsShareable</td><td>1 = region is shareable between multiple bus masters. </td></tr> + <tr><td class="paramname">IsCacheable</td><td>1 = region is cacheable (values may be kept in cache). </td></tr> + <tr><td class="paramname">IsBufferable</td><td>1 = region is bufferable (when using write-back caching). Cacheable but non-bufferable regions use write-through policy. </td></tr> + <tr><td class="paramname">SubRegionDisable</td><td>Sub-region disable field (8 bits). </td></tr> + <tr><td class="paramname">Size</td><td>Region size with values defined under <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga332ed5f8969dd4df6b61c6ae32ec36dc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RASR_EX</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">DisableExec, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">AccessPermission, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">AccessAttributes, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">SubRegionDisable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">Size </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">DisableExec</td><td>Instruction access disable bit, 1= disable instruction fetches. </td></tr> + <tr><td class="paramname">AccessPermission</td><td>Data access permission configures read/write access for User and Privileged mode. Possible values see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr> + <tr><td class="paramname">AccessAttributes</td><td>Memory access attribution, see <a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a>. </td></tr> + <tr><td class="paramname">SubRegionDisable</td><td>Sub-region disable field (8 bits). </td></tr> + <tr><td class="paramname">Size</td><td>Region size with values defined under <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga3fead12dc24a6d00ad53f55a042486ca"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RBAR</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">Region, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">BaseAddress </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This preprocessor function can be used to construct a valid <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> value. The VALID bit is implicitly set to 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">Region</td><td>The region to be configured, number 0 to 15. </td></tr> + <tr><td class="paramname">BaseAddress</td><td>The base address for the region. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga9dcb0afddf4ac351f33f3c7a5169c62c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegion </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear and disable the given MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga7cbc0a4a066ed90e85c8176228235d57"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Disable </td> + <td>(</td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable the MPU. </p> + +</div> +</div> +<a class="anchor" id="ga31406efd492ec9a091a70ffa2d8a42fb"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Enable </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>MPU_CTRL</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">MPU_CTRL</td><td>Additional control settings that configure MPU behaviour</td></tr> + </table> + </dd> +</dl> +<p>The function <a class="el" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a> writes to the register <a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU->CTRL</a> and sets bit ENABLE. The parameter <em>MPU_CTRL</em> provides additional bit values (see table below) that configure the MPU behaviour. For processors that implement an <b>MPU Fault Handler</b> the <a class="el" href="group__NVIC__gr.html">MemoryManagement_IRQn</a> exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.</p> +<p>The following table contains possible values for the parameter <em>MPU_CTRL</em> that set specific bits in register MPU->CTRL. </p> +<table class="doxtable"> +<tr> +<th align="left">Bit </th><th align="left">MPU_CTRL value </th><th align="left">When applied </th><th align="left">When not applied </th></tr> +<tr> +<td align="left">1 </td><td align="left">MPU_CTRL_HFNMIENA_Msk </td><td align="left">Enable MPU during hard fault, NMI, and FAULTMASK handlers execution </td><td align="left">Disable MPU during hard fault, NMI, and FAULTMASK handler execution </td></tr> +<tr> +<td align="left">2 </td><td align="left">MPU_CTRL_PRIVDEFENA_Msk </td><td align="left">Enable default memory map as a background region for privileged access </td><td align="left">Use only MPU region settings </td></tr> +</table> +<p><b>Example:</b></p> +<div class="fragment"><div class="line"><span class="comment">// enable MPU with all region definitions. Exceptions are not protected by MPU.</span></div> +<div class="line"> MPU_Enable (0);</div> +<div class="line"> </div> +<div class="line"><span class="comment">// enable MPU with all region definitions and background regions for privileged access. Exceptions are protected by MPU.</span></div> +<div class="line"> MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gafa27b26d5847fa8e465584e376b6078a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Load </td> + <td>(</td> + <td class="paramtype">MPU_Region_t const * </td> + <td class="paramname"><em>table</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>cnt</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Load the given number of MPU regions from a table. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr> + <tr><td class="paramname">cnt</td><td>Number of regions to be configured.</td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>only up to 16 regions can be handled as the function <a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a> uses the REGION field in <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU->RBAR</a>.</dd></dl> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line"><span class="keyword">const</span> <a class="code" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> mpuTable[3][4] = {</div> +<div class="line"> {</div> +<div class="line"> { .<a class="code" href="structARM__MPU__Region__t.html#aa5e3c6aeaddbc0c283085dc971dd1a22">RBAR</a> = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0UL, 0x08000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(1UL, 0x20000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(2UL, 0x40020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(3UL, 0x40022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div> +<div class="line"> },</div> +<div class="line"> {</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(4UL, 0x08000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(5UL, 0x20000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(6UL, 0x40020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(7UL, 0x40022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div> +<div class="line"> },</div> +<div class="line"> {</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(4UL, 0x18000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(5UL, 0x30000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(6UL, 0x50020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(7UL, 0x50022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div> +<div class="line"> }</div> +<div class="line">};</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> UpdateMpu(uint32_t idx)</div> +<div class="line">{</div> +<div class="line"> <a class="code" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a>(mpuTable[idx], 4);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga16931f9ad84d7289e8218e169ae6db5d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegion </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rbar</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rasr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure an MPU region.</p> +<p>The region number should be contained in the rbar value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rbar</td><td>Value for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> register. </td></tr> + <tr><td class="paramname">rasr</td><td>Value for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> register. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga042ba1a6a1a58795231459ac0410b809"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegionEx </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rbar</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rasr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure the given MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr> + <tr><td class="paramname">rbar</td><td>Value for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> register. </td></tr> + <tr><td class="paramname">rasr</td><td>Value for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> register. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |