From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/group__mpu__functions.html | 576 ++++++++++++++++++++++++++++++ 1 file changed, 576 insertions(+) create mode 100644 docs/Core/html/group__mpu__functions.html (limited to 'docs/Core/html/group__mpu__functions.html') diff --git a/docs/Core/html/group__mpu__functions.html b/docs/Core/html/group__mpu__functions.html new file mode 100644 index 0000000..0803dee --- /dev/null +++ b/docs/Core/html/group__mpu__functions.html @@ -0,0 +1,576 @@ + + + + + +MPU Functions for Armv7-M +CMSIS-Core (Cortex-M): MPU Functions for Armv7-M + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-M) +  Version 5.1.2 +
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CMSIS-Core support for Cortex-M processor-based devices
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+Content | +Data Structures | +Macros | +Functions
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MPU Functions for Armv7-M
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Functions that relate to the Memory Protection Unit. +More...

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+Content

 Define values
 Define values for MPU region setup.
 
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+Data Structures

struct  MPU_Type
 Structure type to access the Memory Protection Unit (MPU). More...
 
struct  ARM_MPU_Region_t
 Setup information of a single MPU Region. More...
 
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+Macros

#define ARM_MPU_RBAR(Region, BaseAddress)
 MPU Region Base Address Register Value. More...
 
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
 MPU Region Attribute and Size Register Value. More...
 
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)
 MPU Region Attribute and Size Register Value. More...
 
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+Functions

__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_CTRL)
 Enable the memory protection unit (MPU) and. More...
 
__STATIC_INLINE void ARM_MPU_Disable ()
 
__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rbar, uint32_t rasr)
 
__STATIC_INLINE void ARM_MPU_SetRegionEx (uint32_t rnr, uint32_t rbar, uint32_t rasr)
 
__STATIC_INLINE void ARM_MPU_Load (MPU_Region_t const *table, uint32_t cnt)
 
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Description

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The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.

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The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.

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Example:

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void main()
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// Set Region 0
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ARM_MPU_SetRegionEx(0UL, 0x08000000UL, MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));
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ARM_MPU_Enable(0);
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// Execute application code that is access protected by the MPU
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ARM_MPU_Disable();
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}
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Macro Definition Documentation

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#define ARM_MPU_RASR( DisableExec,
 AccessPermission,
 TypeExtField,
 IsShareable,
 IsCacheable,
 IsBufferable,
 SubRegionDisable,
 Size 
)
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This macro is used to construct a valid RASR value. The ENABLE bit of the RASR value is implicitly set to 1.

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Parameters
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DisableExecInstruction access disable bit. 1 = disable instruction fetches.
AccessPermissionData access permission configures read/write access for User and Privileged mode. Possible values see ARM_MPU_AP_xxx.
TypeExtFieldType extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
IsShareable1 = region is shareable between multiple bus masters.
IsCacheable1 = region is cacheable (values may be kept in cache).
IsBufferable1 = region is bufferable (when using write-back caching). Cacheable but non-bufferable regions use write-through policy.
SubRegionDisableSub-region disable field (8 bits).
SizeRegion size with values defined under ARM_MPU_REGION_SIZE_xxx.
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#define ARM_MPU_RASR_EX( DisableExec,
 AccessPermission,
 AccessAttributes,
 SubRegionDisable,
 Size 
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This macro is used to construct a valid RASR value. The ENABLE bit of the RASR value is implicitly set to 1.

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Parameters
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DisableExecInstruction access disable bit, 1= disable instruction fetches.
AccessPermissionData access permission configures read/write access for User and Privileged mode. Possible values see ARM_MPU_AP_xxx.
AccessAttributesMemory access attribution, see ARM_MPU_ACCESS_xxx.
SubRegionDisableSub-region disable field (8 bits).
SizeRegion size with values defined under ARM_MPU_REGION_SIZE_xxx.
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#define ARM_MPU_RBAR( Region,
 BaseAddress 
)
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This preprocessor function can be used to construct a valid RBAR value. The VALID bit is implicitly set to 1.

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Parameters
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RegionThe region to be configured, number 0 to 15.
BaseAddressThe base address for the region.
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Function Documentation

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__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
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Clear and disable the given MPU region.

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Parameters
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rnrRegion number to be cleared.
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__STATIC_INLINE void ARM_MPU_Disable ()
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Disable the MPU.

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__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_CTRL)
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Parameters
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MPU_CTRLAdditional control settings that configure MPU behaviour
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The function ARM_MPU_Enable writes to the register MPU->CTRL and sets bit ENABLE. The parameter MPU_CTRL provides additional bit values (see table below) that configure the MPU behaviour. For processors that implement an MPU Fault Handler the MemoryManagement_IRQn exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.

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The following table contains possible values for the parameter MPU_CTRL that set specific bits in register MPU->CTRL.

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Bit MPU_CTRL value When applied When not applied
1 MPU_CTRL_HFNMIENA_Msk Enable MPU during hard fault, NMI, and FAULTMASK handlers execution Disable MPU during hard fault, NMI, and FAULTMASK handler execution
2 MPU_CTRL_PRIVDEFENA_Msk Enable default memory map as a background region for privileged access Use only MPU region settings
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Example:

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// enable MPU with all region definitions. Exceptions are not protected by MPU.
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MPU_Enable (0);
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// enable MPU with all region definitions and background regions for privileged access. Exceptions are protected by MPU.
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MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
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__STATIC_INLINE void ARM_MPU_Load (MPU_Region_t const * table,
uint32_t cnt 
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Load the given number of MPU regions from a table.

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Parameters
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tablePointer to the MPU configuration table.
cntNumber of regions to be configured.
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Note
only up to 16 regions can be handled as the function ARM_MPU_Load uses the REGION field in MPU->RBAR.
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Example:

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const ARM_MPU_Region_t mpuTable[3][4] = {
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{
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{ .RBAR = ARM_MPU_RBAR(0UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
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{ .RBAR = ARM_MPU_RBAR(1UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
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{ .RBAR = ARM_MPU_RBAR(2UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
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{ .RBAR = ARM_MPU_RBAR(3UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
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},
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{
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{ .RBAR = ARM_MPU_RBAR(4UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
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{ .RBAR = ARM_MPU_RBAR(5UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
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{ .RBAR = ARM_MPU_RBAR(6UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
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{ .RBAR = ARM_MPU_RBAR(7UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
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},
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{
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{ .RBAR = ARM_MPU_RBAR(4UL, 0x18000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
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{ .RBAR = ARM_MPU_RBAR(5UL, 0x30000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
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{ .RBAR = ARM_MPU_RBAR(6UL, 0x50020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
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{ .RBAR = ARM_MPU_RBAR(7UL, 0x50022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
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}
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};
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void UpdateMpu(uint32_t idx)
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{
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ARM_MPU_Load(mpuTable[idx], 4);
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}
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__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rbar,
uint32_t rasr 
)
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Configure an MPU region.

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The region number should be contained in the rbar value.

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Parameters
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rbarValue for RBAR register.
rasrValue for RASR register.
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__STATIC_INLINE void ARM_MPU_SetRegionEx (uint32_t rnr,
uint32_t rbar,
uint32_t rasr 
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Configure the given MPU region.

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rnrRegion number to be configured.
rbarValue for RBAR register.
rasrValue for RASR register.
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