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| author | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
|---|---|---|
| committer | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
| commit | 84a7bf753760ad7442d8762d2780560e6a734d96 (patch) | |
| tree | 0285251d0b27ecdc83f2099d3e6fc190ca74c8de /core_cm1.h | |
| parent | e2fd8448cfaf68d2b29f3602a0608054b1d4ee4c (diff) | |
| download | st-cmsis-core-lowfat-84a7bf753760ad7442d8762d2780560e6a734d96.tar.gz st-cmsis-core-lowfat-84a7bf753760ad7442d8762d2780560e6a734d96.tar.bz2 st-cmsis-core-lowfat-84a7bf753760ad7442d8762d2780560e6a734d96.zip | |
Official ARM version: v5.6.0master-subtree-include
Diffstat (limited to 'core_cm1.h')
| -rw-r--r-- | core_cm1.h | 9 |
1 files changed, 6 insertions, 3 deletions
@@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm1.h * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File - * @version V1.0.0 - * @date 23. July 2018 + * @version V1.0.1 + * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -651,7 +651,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -858,6 +860,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ } |