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| author | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
|---|---|---|
| committer | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
| commit | 96d6da4e252b06dcfdc041e7df23e86161c33007 (patch) | |
| tree | a262f59bb1db7ec7819acae435f5049cbe5e2354 /Core_A/Include/cmsis_iccarm.h | |
| parent | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (diff) | |
| download | st-cmsis-core-lowfat-master.tar.gz st-cmsis-core-lowfat-master.tar.bz2 st-cmsis-core-lowfat-master.zip | |
Diffstat (limited to 'Core_A/Include/cmsis_iccarm.h')
| -rw-r--r-- | Core_A/Include/cmsis_iccarm.h | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/Core_A/Include/cmsis_iccarm.h b/Core_A/Include/cmsis_iccarm.h index bb0248d..7d44107 100644 --- a/Core_A/Include/cmsis_iccarm.h +++ b/Core_A/Include/cmsis_iccarm.h @@ -1,13 +1,14 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.6 - * @date 02. March 2018 + * @version V5.0.7 + * @date 15. May 2019 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2018-2019 Arm Limited // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -69,6 +70,10 @@ #define __ASM __asm #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + #ifndef __INLINE #define __INLINE inline #endif @@ -109,7 +114,12 @@ #endif #ifndef __RESTRICT - #define __RESTRICT __restrict + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif #endif #ifndef __STATIC_INLINE @@ -542,10 +552,12 @@ void __FPU_Enable(void) #endif //Initialise FPSCR to a known state - " VMRS R2,FPSCR \n" - " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R2,R2,R3 \n" - " VMSR FPSCR,R2 \n"); + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); } |