summaryrefslogtreecommitdiff
path: root/Core_A/Include/cmsis_armcc.h
diff options
context:
space:
mode:
authorrihab kouki <rihab.kouki@st.com>2020-07-28 11:24:49 +0100
committerrihab kouki <rihab.kouki@st.com>2020-07-28 11:24:49 +0100
commit96d6da4e252b06dcfdc041e7df23e86161c33007 (patch)
treea262f59bb1db7ec7819acae435f5049cbe5e2354 /Core_A/Include/cmsis_armcc.h
parent9f95ff5b6ba01db09552b84a0ab79607060a2666 (diff)
downloadst-cmsis-core-lowfat-master.tar.gz
st-cmsis-core-lowfat-master.tar.bz2
st-cmsis-core-lowfat-master.zip
Official ARM version: v5.6.0HEADmaster
Diffstat (limited to 'Core_A/Include/cmsis_armcc.h')
-rw-r--r--Core_A/Include/cmsis_armcc.h17
1 files changed, 10 insertions, 7 deletions
diff --git a/Core_A/Include/cmsis_armcc.h b/Core_A/Include/cmsis_armcc.h
index 313d743..ec17393 100644
--- a/Core_A/Include/cmsis_armcc.h
+++ b/Core_A/Include/cmsis_armcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.0.2
- * @date 10. January 2018
+ * @version V1.0.3
+ * @date 15. May 2019
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -86,6 +86,9 @@
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
/* ########################## Core Instruction Access ######################### */
/**
@@ -533,10 +536,10 @@ __STATIC_INLINE __ASM void __FPU_Enable(void)
ENDIF
//Initialise FPSCR to a known state
- VMRS R2,FPSCR
- LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
- AND R2,R2,R3
- VMSR FPSCR,R2
+ VMRS R1,FPSCR
+ LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ AND R1,R1,R2
+ VMSR FPSCR,R1
BX LR
}