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| author | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
|---|---|---|
| committer | rihab kouki <rihab.kouki@st.com> | 2020-07-28 11:24:49 +0100 |
| commit | 96d6da4e252b06dcfdc041e7df23e86161c33007 (patch) | |
| tree | a262f59bb1db7ec7819acae435f5049cbe5e2354 /Core/Include/core_sc000.h | |
| parent | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (diff) | |
| download | st-cmsis-core-lowfat-master.tar.gz st-cmsis-core-lowfat-master.tar.bz2 st-cmsis-core-lowfat-master.zip | |
Diffstat (limited to 'Core/Include/core_sc000.h')
| -rw-r--r-- | Core/Include/core_sc000.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/Core/Include/core_sc000.h b/Core/Include/core_sc000.h index 9b67c92..cf92577 100644 --- a/Core/Include/core_sc000.h +++ b/Core/Include/core_sc000.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 28. May 2018 + * @version V5.0.6 + * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -750,7 +750,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -904,6 +906,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ } |