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/* Megumin LED display firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "global.h"
uint32_t pcg32_random_r() {
// *Really* minimal PCG32 code / (c) 2014 M.E. O'Neill / pcg-random.org
// Licensed under Apache License 2.0 (NO WARRANTY, etc. see website)
static uint64_t state = 0xbc422715d3aef60f;
static uint64_t inc = 0x6605e3bc6d1a869b;
uint64_t oldstate = state;
// Advance internal state
state = oldstate * 6364136223846793005ULL + (inc|1);
// Calculate output function (XSH RR), uses old state for max ILP
uint32_t xorshifted = ((oldstate >> 18u) ^ oldstate) >> 27u;
uint32_t rot = oldstate >> 59u;
return (xorshifted >> rot) | (xorshifted << ((-rot) & 31));
}
int main(void){
/* We're starting out from HSI@8MHz */
SystemCoreClockUpdate();
SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk); /* Disable for now */
for (int i=0; i<50000; i++)
asm volatile ("nop");
/* Turn on lots of neat things */
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_TIM4EN;
GPIOC->CRH |=
(0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
GPIOB->CRL |=
(2<<GPIO_CRL_CNF5_Pos) | (2<<GPIO_CRL_MODE5_Pos); /* PB5 - TIM3_CH2 */
AFIO->MAPR |= (2 << AFIO_MAPR_TIM3_REMAP_Pos); /* Map TIM3_CH2 to PB5 */
GPIOB->CRH |=
(2<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos) /* PB8 - TIM4_CH3 */
| (2<<GPIO_CRH_CNF9_Pos) | (2<<GPIO_CRH_MODE9_Pos); /* PB9 - TIM4_CH4 */
GPIOC->ODR |= 1<<13; /* LED */
TIM3->SMCR = (3<<TIM_SMCR_TS_Pos) | (6 << TIM_SMCR_SMS_Pos);
TIM4->CR2 = (4<<TIM_CR2_MMS_Pos);
int period = 0xffff;
int thr[3] = {20000, 30000};
int overlap = 1000;
TIM4->CCR3 = thr[0];
TIM4->CCR4 = thr[1];
TIM4->CCR1 = thr[0];
TIM3->CCR2 = thr[1] - thr[0];
TIM3->ARR = 0xfffe;
TIM4->ARR = 0xffff;
TIM3->CCER = TIM_CCER_CC2E;
TIM3->CCMR1 = (0<<TIM_CCMR1_CC2S_Pos) | TIM_CCMR1_OC2PE | (6<<TIM_CCMR1_OC2M_Pos);
TIM4->CCER = TIM_CCER_CC3E | TIM_CCER_CC4E | TIM_CCER_CC1E | TIM_CCER_CC3P | TIM_CCER_CC4P;
TIM4->CCMR1 = (0<<TIM_CCMR1_CC1S_Pos) | TIM_CCMR1_OC1PE | (7<<TIM_CCMR1_OC1M_Pos);
TIM4->CCMR2 = (0<<TIM_CCMR2_CC4S_Pos) | TIM_CCMR2_OC4PE | (6<<TIM_CCMR2_OC4M_Pos) \
| (0<<TIM_CCMR2_CC3S_Pos) | TIM_CCMR2_OC3PE | (7<<TIM_CCMR2_OC3M_Pos);
TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_OPM;
TIM4->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN;
for (;;) {
}
}
void gdb_dump(void) {
/* debugger hook */
}
void NMI_Handler(void) {
asm volatile ("bkpt");
}
void HardFault_Handler(void) __attribute__((naked));
void HardFault_Handler() {
asm volatile ("bkpt");
}
void SVC_Handler(void) {
asm volatile ("bkpt");
}
void PendSV_Handler(void) {
asm volatile ("bkpt");
}
void SysTick_Handler(void) {
asm volatile ("bkpt");
}
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