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2017-03-22working temp/humi stop/repeated stuff on f0Karl Palsson1-24/+32
needs cleanup and remerge with f4/l1
2017-03-22use transfer style for serial number readingKarl Palsson1-4/+6
2017-03-22f0 working with repeated start properly. need to squish lots of thisKarl Palsson3-26/+334
like, you left the f0 makefiles out earlier, and it's all boring history anwyay
2017-03-09i2c: draft api of "set speed 100k" commonKarl Palsson1-17/+23
Only needs the input clock in megahz.
2017-03-08i2c-master: first hack working on f0Karl Palsson1-5/+25
read_i2c and write_i2c are not flexible enough, and terribly named. they're going to have to go, but they're a nice start for some things.
2017-03-08i2c-master: working on l1 too.Karl Palsson5-8/+108
Needs retest on f4. then ready to move to new hardware
2017-03-01i2c-master: tidy up more.Karl Palsson5-34/+39
Still f4 only, but cleaner, and more testing with sigrok for verification
2017-02-21i2c-master: start extracting out i2c codeKarl Palsson3-123/+201
Working on f4 with an external sht21 i2c sensor. Still lots of f4 specifics yet. But, progress.
2017-02-21i2c-master: start progressing to extracting common i2c codeKarl Palsson5-18/+102
2017-02-21i2c: Initial stub import of old f4 codeKarl Palsson3-0/+246
Currently (despite docs) is an import of code reading the onboard i2c peripheral
2017-02-21usb-rs485: more docsKarl Palsson1-0/+3
2017-02-21usb-rs485: update to latest library masterKarl Palsson2-5/+4
2016-10-03usb-rs485: enable rs485 mode.Karl Palsson2-16/+12
Tested on the f1 with a LA only, but traces look good and as expected. future work to actually hook it up to a rs485 device.
2016-09-30usb-rs485: update readmeKarl Palsson1-0/+9
2016-09-30usb-serial: functional f4Karl Palsson2-2/+48
Add stubs based on f1, and include irq timing pin
2016-09-30usb-serial: f1: try and diagnose corruption in rx pathKarl Palsson1-0/+1
2016-09-30usb-serial: functional on f1.Karl Palsson7-111/+379
2016-09-27oocd: move stm32f1 config file to commonKarl Palsson2-18/+1
2016-09-26ubs-serial-rs485: First solidly working version.Karl Palsson9-0/+887
Needs major refactoring to split out the _actual_ arch dependent pieces. Needs parity and more complete baud rate support. Needs rs485 support.
2016-09-26adc-power: update makefiles with work lying aroundKarl Palsson7-24/+146
2016-09-11adc-power: include f1 testsKarl Palsson3-0/+128
2016-09-09adc-power: Calling adc_power_off twice should be safeKarl Palsson1-0/+2
but, it's not on f3 at present. See https://github.com/libopencm3/libopencm3/issues/654 and https://github.com/libopencm3/libopencm3/pull/662
2016-09-09adc-power: f3 adc peripheral takes over gpios automatically?Karl Palsson1-3/+5
Doesn't seem to have any impact when just hooking up a pot to the pins at least.
2016-09-09adc-power: add oocd file for f3 discoKarl Palsson1-0/+12
2016-09-09adc-power: add f4 oocd configKarl Palsson1-0/+12
2016-09-09qemu test sample from daniellinux:Karl Palsson3-0/+118
soruced originally from: https://github.com/libopencm3/libopencm3/pull/613 edited to drop the use of bin files, and switch to devices.data
2016-09-09switch to using devices.data linker generationKarl Palsson4-23/+8
Still using my own private rules, but now using the linker script generator so no need to keep expanding on including .ld files in core libopencm3
2016-08-19rcc-legal-ranges: run through a range of clocksKarl Palsson3-30/+119
blink fast/slow for each clock configuration tested, then finish by blinking idly. As of this commit, this test fails quickly on most L1 boards tested. An update to libopencm3 is required to fix this.
2016-08-18rcc-legal-ranges: initial l1 setupKarl Palsson3-0/+107
Doesn't fail on my l1 disco unfortunately. (silicon rev X) Does fail on a custom board with silicon rev V
2016-03-30adc: hacks to get it up and running for L4Karl Palsson2-3/+15
2016-03-30adc: document where debug output goesKarl Palsson1-0/+4
2016-03-30adc: use single float literalsKarl Palsson1-3/+3
Dramatic performance improvement on m4f cores, ~1600->80 cycles
2016-03-30adc: f4: update for new namingKarl Palsson1-1/+1
2016-03-14fix l4 to run at 48Mhz and with a clockKarl Palsson2-0/+11
2016-03-04attempt actual adc on l4Karl Palsson3-5/+23
(insufficient,needs clocks yet)
2016-03-04f3: use new rcc namesKarl Palsson1-8/+11
2016-03-04use new names for SMPRx definesKarl Palsson1-2/+6
2016-03-04l4 miniblinkKarl Palsson2-0/+77
We'll build up to the adc temp sensor from here
2016-03-04f0 working (one fixme)Karl Palsson3-3/+89
need scan mode upstream?
2015-11-03WIP: f0 adc buildKarl Palsson1-1/+11
2015-11-03f3 temp sensor workingKarl Palsson3-10/+15
2015-11-03f4: proper float/int temp readingsKarl Palsson2-41/+49
2015-10-28f3: wip continuesKarl Palsson2-14/+131
2015-10-17WIP: adc-power f3Karl Palsson2-0/+80
needs rcc fixups
2015-10-17adc-power: f4: use correct path to linkerKarl Palsson1-1/+1
Don't escape the project!
2015-10-17stub adc on/off test code.Karl Palsson4-0/+215
Needs a pot on PA0, should get the temperature input working as well.
2015-10-16purpose of first testKarl Palsson1-0/+8
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