rcc-legal-ranges: initial l1 setup

Doesn't fail on my l1 disco unfortunately. (silicon rev X)
Does fail on a custom board with silicon rev V

3 files changed, 107 insertions, 0 deletions

diff --git a/tests/rcc-legal-ranges/Makefile.stm32l1-generic b/tests/rcc-legal-ranges/Makefile.stm32l1-generic
new file mode 100644
index 0000000..bdb721e
--- /dev/null
+++ b/tests/rcc-legal-ranges/Makefile.stm32l1-generic
@@ -0,0 +1,27 @@
+
+BOARD = stm32l1-generic
+PROJECT = rcc-legal-ranges-$(BOARD)
+BUILD_DIR = bin-$(BOARD)
+
+SHARED_DIR = ../../shared
+
+CFILES = main-$(BOARD).c
+#CFILES += trace.c trace_stdio.c
+
+VPATH += $(SHARED_DIR)
+
+INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR))
+
+OPENCM3_DIR=../../libopencm3/
+
+### This section can go to an arch shared rules eventually...
+LDSCRIPT = $(OPENCM3_DIR)/lib/stm32/l1/stm32l15xx6.ld # pessimistic ;)
+OPENCM3_LIB = opencm3_stm32l1
+OPENCM3_DEFS = -DSTM32L1
+FP_FLAGS ?=
+ARCH_FLAGS = -mthumb -mcpu=cortex-m3 $(FP_FLAGS)
+# Use the base targets, as we're playing with clocking too much for swo
+OOCD_INTERFACE = stlink-v2
+OOCD_TARGET = stm32l1
+
+include ../../rules.mk
diff --git a/tests/rcc-legal-ranges/README.md b/tests/rcc-legal-ranges/README.md
new file mode 100644
index 0000000..2720e56
--- /dev/null
+++ b/tests/rcc-legal-ranges/README.md
@@ -0,0 +1,13 @@
+
+Tests whether legal clock config structures can actually be used.
+This primarily is testing whether the order of steps taken for
+turning on and selecting different clocks, power ranges and flash
+wait state configuration are robust enough.
+
+## PASSING
+The board should issue a series of blinks at various rates before
+settling on a steady rate
+
+## FAILING
+The board stops blinking at any point in the sequence
+
diff --git a/tests/rcc-legal-ranges/main-stm32l1-generic.c b/tests/rcc-legal-ranges/main-stm32l1-generic.c
new file mode 100644
index 0000000..4418827
--- /dev/null
+++ b/tests/rcc-legal-ranges/main-stm32l1-generic.c
@@ -0,0 +1,67 @@
+/*
+ * Aug 2016 Karl Palsson <karlp@tweak.net.au>
+ */
+
+#include <libopencm3/stm32/flash.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/rcc.h>
+
+/* Disco board is b6 */
+#define LEDPORT GPIOB
+#define LEDPIN GPIO6
+
+/**
+ * blink led count times, with vile hack * 1000 asm nops
+ */
+static void hack_blink(int count, int hack)
+{
+	for (int i = 0; i < count; i++) {
+		gpio_toggle(LEDPORT, LEDPIN);
+		for (int k = 0; k < hack * 1000; k++) {
+			__asm__("nop");
+		}
+	}
+}
+
+int main(void)
+{
+	int i;
+	int j = 0;
+	/* Allow leds on any port */
+	RCC_AHBENR |= 0xff;
+	gpio_mode_setup(LEDPORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LEDPIN);
+	/* blink twice with slow msi reset clock */
+	hack_blink(4, 60);
+
+	/* step forward to HSI/2, 8Mhz */
+	struct rcc_clock_scale v2_8low = {
+                .hpre = RCC_CFGR_HPRE_SYSCLK_DIV2,
+                .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+                .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+                .voltage_scale = PWR_SCALE2,
+                .flash_config = FLASH_ACR_LATENCY_0WS,
+		.ahb_frequency = 8000000,
+                .apb1_frequency = 8000000,
+                .apb2_frequency = 8000000,
+	};
+	rcc_clock_setup_hsi(&v2_8low);
+	/* blink twice again, different rate */
+	hack_blink(4, 60);
+
+	/* step forward to HSI->PLL@32Mhz, range 1 */
+	rcc_clock_setup_pll(&rcc_clock_config[RCC_CLOCK_VRANGE1_HSI_PLL_32MHZ]);
+	/* blink twice again */
+	hack_blink(4, 400);
+
+	/* back down again */
+	rcc_clock_setup_hsi(&v2_8low);
+	hack_blink(4, 60);
+
+	/* just keep blinking */
+	while (1) {
+		hack_blink(1, 400);
+	}
+
+	return 0;
+}