olsndot.git - olsndot: 32-channel high fidelity 12V LED tape driver with RS485 control

Age	Commit message (Collapse)	Author	Files	Lines
2016-09-26	ubs-serial-rs485: First solidly working version.	Karl Palsson	9	-0/+887
	Needs major refactoring to split out the _actual_ arch dependent pieces. Needs parity and more complete baud rate support. Needs rs485 support.
2016-09-26	adc-power: update makefiles with work lying around	Karl Palsson	7	-24/+146

2016-09-11	adc-power: include f1 tests	Karl Palsson	3	-0/+128

2016-09-09	adc-power: Calling adc_power_off twice should be safe	Karl Palsson	1	-0/+2
	but, it's not on f3 at present. See https://github.com/libopencm3/libopencm3/issues/654 and https://github.com/libopencm3/libopencm3/pull/662
2016-09-09	adc-power: f3 adc peripheral takes over gpios automatically?	Karl Palsson	1	-3/+5
	Doesn't seem to have any impact when just hooking up a pot to the pins at least.
2016-09-09	adc-power: add oocd file for f3 disco	Karl Palsson	1	-0/+12

2016-09-09	adc-power: add f4 oocd config	Karl Palsson	1	-0/+12

2016-09-09	qemu test sample from daniellinux:	Karl Palsson	3	-0/+118
	soruced originally from: https://github.com/libopencm3/libopencm3/pull/613 edited to drop the use of bin files, and switch to devices.data
2016-09-09	switch to using devices.data linker generation	Karl Palsson	4	-23/+8
	Still using my own private rules, but now using the linker script generator so no need to keep expanding on including .ld files in core libopencm3
2016-08-19	rcc-legal-ranges: run through a range of clocks	Karl Palsson	3	-30/+119
	blink fast/slow for each clock configuration tested, then finish by blinking idly. As of this commit, this test fails quickly on most L1 boards tested. An update to libopencm3 is required to fix this.
2016-08-18	rcc-legal-ranges: initial l1 setup	Karl Palsson	3	-0/+107
	Doesn't fail on my l1 disco unfortunately. (silicon rev X) Does fail on a custom board with silicon rev V
2016-03-30	adc: hacks to get it up and running for L4	Karl Palsson	2	-3/+15

2016-03-30	adc: document where debug output goes	Karl Palsson	1	-0/+4

2016-03-30	adc: use single float literals	Karl Palsson	1	-3/+3
	Dramatic performance improvement on m4f cores, ~1600->80 cycles
2016-03-30	adc: f4: update for new naming	Karl Palsson	1	-1/+1

2016-03-14	fix l4 to run at 48Mhz and with a clock	Karl Palsson	2	-0/+11

2016-03-04	attempt actual adc on l4	Karl Palsson	3	-5/+23
	(insufficient,needs clocks yet)
2016-03-04	f3: use new rcc names	Karl Palsson	1	-8/+11

2016-03-04	use new names for SMPRx defines	Karl Palsson	1	-2/+6

2016-03-04	l4 miniblink	Karl Palsson	2	-0/+77
	We'll build up to the adc temp sensor from here
2016-03-04	f0 working (one fixme)	Karl Palsson	3	-3/+89
	need scan mode upstream?
2015-11-03	WIP: f0 adc build	Karl Palsson	1	-1/+11

2015-11-03	f3 temp sensor working	Karl Palsson	3	-10/+15

2015-11-03	f4: proper float/int temp readings	Karl Palsson	2	-41/+49

2015-10-28	f3: wip continues	Karl Palsson	2	-14/+131

2015-10-17	WIP: adc-power f3	Karl Palsson	2	-0/+80
	needs rcc fixups
2015-10-17	adc-power: f4: use correct path to linker	Karl Palsson	1	-1/+1
	Don't escape the project!
2015-10-17	stub adc on/off test code.	Karl Palsson	4	-0/+215
	Needs a pot on PA0, should get the temperature input working as well.
2015-10-16	purpose of first test	Karl Palsson	1	-0/+8