diff options
Diffstat (limited to 'firmware/main.c')
| -rw-r--r-- | firmware/main.c | 45 |
1 files changed, 21 insertions, 24 deletions
diff --git a/firmware/main.c b/firmware/main.c index 7b9a627..e6fa20a 100644 --- a/firmware/main.c +++ b/firmware/main.c @@ -53,44 +53,41 @@ uint32_t sys_time_seconds = 0; * longest cycle. Here too the above caveats apply. * * This value is in TIM1/TIM3 timer counts. */ -#define ADC_PRETRIGGER 150 /* trigger with about 12us margin to TIM1 CC IRQ */ - -/* Bit timing base value. This is the lowes bit interval used */ -#define PERIOD_BASE 4 +#define ADC_PRETRIGGER 300 /* trigger with about 12us margin to TIM1 CC IRQ */ /* This value is a constant offset added to every bit period to allow for the timer IRQ handler to execute. This is set * empirically using a debugger and a logic analyzer. */ -#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 120 +#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 240 /* This is the same as above, but for the reset cycle of the bit period. */ -#define RESET_PERIOD_LENGTH 40 +#define RESET_PERIOD_LENGTH 80 /* Defines for brevity */ #define A TIMER_CYCLES_FOR_SPI_TRANSMISSIONS -#define B PERIOD_BASE +#define B 40 /* This is a constant offset containing some empirically determined correction values */ -#define C (1 /* reset pulse comp */ - 3 /* analog snafu comp */) +#define C 0 /* This lookup table maps bit positions to timer period values. This is a lookup table to allow for the compensation for * non-linear effects of ringing at lower bit durations. */ static uint16_t timer_period_lookup[NBITS] = { /* LSB here */ - A + (B<< 0) - C, - A + (B<< 1) - C, - A + (B<< 2) - C, - A + (B<< 3) - C, - A + (B<< 4) - C, - A + (B<< 5) - C, - A + (B<< 6) - C, - A + (B<< 7) - C, - A + (B<< 8) - C, - A + (B<< 9) - C, - A + (B<<10) - C, - A + (B<<11) - C, - A + (B<<12) - C, - A + (B<<13) - C, + A + 1, + A + 3, + A + 10, + A + 29, + A + 70, + A - C + (B<< 2), + A - C + (B<< 3), + A - C + (B<< 4), + A - C + (B<< 5), + A - C + (B<< 6), + A - C + (B<< 7), + A - C + (B<< 8), + A - C + (B<< 9), + A - C + (B<<10), /* MSB here */ }; @@ -182,7 +179,7 @@ int main(void) { /* Configure TIM1 for display strobe generation */ TIM1->CR1 = TIM_CR1_ARPE; - TIM1->PSC = 1; /* Prescale by 2, resulting in a 15MHz timer frequency and 66.7ns timer step size. */ + TIM1->PSC = 0; /* Prescale by 2, resulting in a 15MHz timer frequency and 66.7ns timer step size. */ /* CH2 - clear/!MR, CH3 - strobe/STCP */ TIM1->CCMR2 = (6<<TIM_CCMR2_OC3M_Pos) | TIM_CCMR2_OC3PE | (6<<TIM_CCMR2_OC4M_Pos); TIM1->CCER |= TIM_CCER_CC3E | TIM_CCER_CC3NE | TIM_CCER_CC3P | TIM_CCER_CC3NP | TIM_CCER_CC4E; @@ -306,7 +303,7 @@ void TIM1_BRK_UP_TRG_COM_IRQHandler(void) { /* Set up the following reset pulse cycle. This cycle is short as it only needs to be long enough for the below * part of this ISR handler routine to run. */ TIM1->ARR = RESET_PERIOD_LENGTH; - TIM1->CCR3 = 1; /* This value is fixed to produce a very short reset pulse. IOs, PCB and shift registers all can + TIM1->CCR3 = 2; /* This value is fixed to produce a very short reset pulse. IOs, PCB and shift registers all can easily handle this. */ } else { /* Set up everything for the data cycle of the *next* period. The timer is set to count from 0 to ARR. ARR and |