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author | Karl Palsson <karlp@tweak.net.au> | 2017-03-01 23:30:59 +0000 |
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committer | Karl Palsson <karlp@tweak.net.au> | 2017-03-08 23:05:52 +0000 |
commit | d6e9b188c71131cf0745b3b25d033a5e16db886e (patch) | |
tree | a752d81785f382636ac52e0ef6626172783da9b1 /tests/i2c-master/i2c-master.c | |
parent | 12f454b41b8d64fb22a55ba9cd748f62ec4f34e9 (diff) | |
download | olsndot-d6e9b188c71131cf0745b3b25d033a5e16db886e.tar.gz olsndot-d6e9b188c71131cf0745b3b25d033a5e16db886e.tar.bz2 olsndot-d6e9b188c71131cf0745b3b25d033a5e16db886e.zip |
i2c-master: working on l1 too.
Needs retest on f4. then ready to move to new hardware
Diffstat (limited to 'tests/i2c-master/i2c-master.c')
-rw-r--r-- | tests/i2c-master/i2c-master.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/tests/i2c-master/i2c-master.c b/tests/i2c-master/i2c-master.c index 50beda8..5f13ddc 100644 --- a/tests/i2c-master/i2c-master.c +++ b/tests/i2c-master/i2c-master.c @@ -33,14 +33,11 @@ void i2cm_init(void) // i2c_enable_ack(hw_details.periph); /* NO ACK FOR SHT21! */ //i2c_set_dutycycle(hw_details.periph, I2C_CCR_DUTY_DIV2); /* default, no need to do this really */ - /* --------- board specific settings! */ - // TODO - rcc_apb2_clock / 1000000 and rounded somehow nicely? - i2c_set_clock_frequency(hw_details.periph, I2C_CR2_FREQ_42MHZ); - /* 42MHz / (100kHz * 2) */ - i2c_set_ccr(hw_details.periph, 210); - /* standard mode, freqMhz+1*/ - i2c_set_trise(hw_details.periph, 43); - /* --------- end of board specific settings!*/ + i2c_set_clock_frequency(hw_details.periph, hw_details.i2c_clock_megahz); + /* x Mhz / (100kHz * 2) */ + i2c_set_ccr(hw_details.periph, hw_details.i2c_clock_megahz * 5); + /* Sm mode, (100kHz) freqMhz + 1 */ + i2c_set_trise(hw_details.periph, hw_details.i2c_clock_megahz + 1); i2c_peripheral_enable(hw_details.periph); } |