f3: use new rcc names

1 files changed, 11 insertions, 8 deletions

diff --git a/tests/adc-power/main-stm32f3-disco.c b/tests/adc-power/main-stm32f3-disco.c
index 6ce40a8..ac678b1 100644
--- a/tests/adc-power/main-stm32f3-disco.c
+++ b/tests/adc-power/main-stm32f3-disco.c
@@ -28,17 +28,18 @@ typedef struct {
 	uint8_t ppre2;
 	uint32_t apb1_frequency;
 	uint32_t apb2_frequency;
+	uint32_t ahb_frequency;
 } rcc_clock_scale_t;
 
 static void rcc_clock_setup_pll_f3_special(const rcc_clock_scale_t *clock)
 {
 	/* Turn on the appropriate source for the PLL */
 	// TODO, some f3's have extra bits here
-	enum osc my_osc;
+	enum rcc_osc my_osc;
 	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_PREDIV) {
-		my_osc = HSE;
+		my_osc = RCC_HSE;
 	} else {
-		my_osc = HSI;
+		my_osc = RCC_HSI;
 	}
 	rcc_osc_on(my_osc);
 	while (!rcc_is_osc_ready(my_osc));
@@ -54,22 +55,23 @@ static void rcc_clock_setup_pll_f3_special(const rcc_clock_scale_t *clock)
 	rcc_set_ppre1(clock->ppre1);
 	rcc_set_ppre2(clock->ppre2);
 
-	rcc_osc_off(PLL);
-	while (rcc_is_osc_ready(PLL));
+	rcc_osc_off(RCC_PLL);
+	while (rcc_is_osc_ready(RCC_PLL));
 	rcc_set_pll_source(clock->pll_source);
 	rcc_set_pll_multiplier(clock->pll_mul);
 	// TODO - iff pll_div != 0, then maybe we're on a target that 
 	// has the dividers?
 
 	/* Enable PLL oscillator and wait for it to stabilize. */
-	rcc_osc_on(PLL);
-	while (!rcc_is_osc_ready(PLL));
+	rcc_osc_on(RCC_PLL);
+	while (!rcc_is_osc_ready(RCC_PLL));
 
 	/* Select PLL as SYSCLK source. */
 	rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
-	rcc_wait_for_sysclk_status(PLL);
+	rcc_wait_for_sysclk_status(RCC_PLL);
 
 	/* Set the peripheral clock frequencies used. */
+	rcc_ahb_frequency = clock->ahb_frequency;
 	rcc_apb1_frequency = clock->apb1_frequency;
 	rcc_apb2_frequency = clock->apb2_frequency;
 }
@@ -85,6 +87,7 @@ static void setup_clocks(void)
 		.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS,
 		.apb1_frequency = 36000000,
 		.apb2_frequency = 72000000,
+		.ahb_frequency = 72000000,
 	};
 
 	rcc_clock_setup_pll_f3_special(&clock_full_hse8mhz);