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| author | Karl Palsson <karlp@tweak.net.au> | 2016-03-30 17:24:12 +0000 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2016-03-30 17:24:12 +0000 |
| commit | bcdf3f89437547f2600c1eb53418909c8f47c6f9 (patch) | |
| tree | 78800f38101bbd36f82db29ac0dc5d46005fede4 /tests/adc-power/adc-power.c | |
| parent | 96bbee9af950433a74dbbf7079081f6ea9d21c53 (diff) | |
| download | olsndot-bcdf3f89437547f2600c1eb53418909c8f47c6f9.tar.gz olsndot-bcdf3f89437547f2600c1eb53418909c8f47c6f9.tar.bz2 olsndot-bcdf3f89437547f2600c1eb53418909c8f47c6f9.zip | |
adc: hacks to get it up and running for L4
Diffstat (limited to 'tests/adc-power/adc-power.c')
| -rw-r--r-- | tests/adc-power/adc-power.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/tests/adc-power/adc-power.c b/tests/adc-power/adc-power.c index 2d7f310..9b6df07 100644 --- a/tests/adc-power/adc-power.c +++ b/tests/adc-power/adc-power.c @@ -39,7 +39,7 @@ #define SAMPLE_TIME_VREF SAMPLE_TIME_TEMP #define SEPARATE_VREF 0 #elif defined(STM32L4) -#define SAMPLE_TIME_BASIC ADC_SMPR_SMP_47DOT5CYC +#define SAMPLE_TIME_BASIC ADC_SMPR_SMP_247DOT5CYC #define SAMPLE_TIME_TEMP ADC_SMPR_SMP_247DOT5CYC #define SAMPLE_TIME_VREF SAMPLE_TIME_TEMP #else @@ -68,6 +68,11 @@ void adc_power_init(void) ADC_CR(ADC1) &= ~ADC_CR_DEEPPWD; RCC_CCIPR |= 3 << 28; // system clock as adc clock. (with CKMODE == 0) adc_enable_regulator(ADC1); + + ADC_CR(ADC1) &= ~ADC_CR_ADCALDIF; + ADC_CR(ADC1) |= ADC_CR_ADCAL; + while (ADC_CR(ADC1) & ADC_CR_ADCAL); + #else rcc_periph_clock_enable(RCC_ADC1); @@ -137,7 +142,7 @@ void adc_power_task_up(void) { * I mean, we're going to do some conversions right? */ adc_set_single_conversion_mode(ADC1); TIM_CNT(TIMER) = 0; - unsigned int v1 = read_adc_naiive(1); + unsigned int v1 = read_adc_naiive(1); // 8 for l4! unsigned int v5 = read_adc_naiive(5); unsigned int temp_adc = read_adc_naiive(ADC_CHANNEL_TEMP); unsigned int vref_adc = read_adc_naiive(ADC_CHANNEL_VREF); |