WIP: hardware test partner round 1

Not sure which kicad files are necessary and which are local yet!

Goal: fixed "host" board (this board) with socket for _any_ Nucleo64 st
board, giving access to test:
* DAC->ADC (both directions)
* I2C (both directions)
* SPI (both directions)
* Uart (both directions)

a socket for a cheap fx2 based logic analyser will be included, so that
sigrok can be used to capture tests of the actual line states.

1 files changed, 36 insertions, 0 deletions

diff --git a/hw1/Socket_Arduino_Uno.pretty/Socket_Strip_Arduino_1x10.kicad_mod b/hw1/Socket_Arduino_Uno.pretty/Socket_Strip_Arduino_1x10.kicad_mod
new file mode 100644
index 0000000..a846466
--- /dev/null
+++ b/hw1/Socket_Arduino_Uno.pretty/Socket_Strip_Arduino_1x10.kicad_mod
@@ -0,0 +1,36 @@
+(module Socket_Strip_Arduino_1x10 (layer F.Cu) (tedit 551AF8D9)
+  (descr "Through hole socket strip")
+  (tags "socket strip")
+  (fp_text reference REF** (at 0 -5.1) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value Socket_Strip_Arduino_1x10 (at 0 -3.1) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start -1.75 -1.75) (end -1.75 1.75) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 24.65 -1.75) (end 24.65 1.75) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -1.75 -1.75) (end 24.65 -1.75) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -1.75 1.75) (end 24.65 1.75) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 1.27 1.27) (end 24.13 1.27) (layer F.SilkS) (width 0.15))
+  (fp_line (start 24.13 1.27) (end 24.13 -1.27) (layer F.SilkS) (width 0.15))
+  (fp_line (start 24.13 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
+  (fp_line (start -1.55 1.55) (end 0 1.55) (layer F.SilkS) (width 0.15))
+  (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
+  (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
+  (fp_line (start -1.55 -1.55) (end -1.55 1.55) (layer F.SilkS) (width 0.15))
+  (pad 1 thru_hole oval (at 0 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 2 thru_hole oval (at 2.54 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 3 thru_hole oval (at 5.08 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 4 thru_hole oval (at 7.62 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 5 thru_hole oval (at 10.16 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 6 thru_hole oval (at 12.7 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 7 thru_hole oval (at 15.24 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 8 thru_hole oval (at 17.78 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 9 thru_hole oval (at 20.32 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (pad 10 thru_hole oval (at 22.86 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
+  (model ${KIPRJMOD}/Socket_Arduino_Uno.3dshapes/Socket_header_Arduino_1x10.wrl
+    (at (xyz 0.45 0 0))
+    (scale (xyz 1 1 1))
+    (rotate (xyz 0 0 180))
+  )
+)