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| author | Karl Palsson <karlp@tweak.net.au> | 2017-11-17 23:00:50 +0000 |
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| committer | Karl Palsson <karlp@tweak.net.au> | 2017-11-17 23:00:50 +0000 |
| commit | 9994a66a3e46534c1a12d6136ae5b894ca4f2cf5 (patch) | |
| tree | eea0d0e30e426ffb49c7409f7fcd92609a964309 /hw1/README | |
| parent | 8366c945925a223dfb38786d4336394e5efc7114 (diff) | |
| download | olsndot-9994a66a3e46534c1a12d6136ae5b894ca4f2cf5.tar.gz olsndot-9994a66a3e46534c1a12d6136ae5b894ca4f2cf5.tar.bz2 olsndot-9994a66a3e46534c1a12d6136ae5b894ca4f2cf5.zip | |
hw1: schematic "finished" ?
have I committed enough files for others to even open this?
Diffstat (limited to 'hw1/README')
| -rw-r--r-- | hw1/README | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/hw1/README b/hw1/README new file mode 100644 index 0000000..6a5ac53 --- /dev/null +++ b/hw1/README @@ -0,0 +1,8 @@ +This is a board designed to receive nucleo64 (and maybe 32) boards +to be test TARGETS. The stm32l1 on _this_ board is reprogrammed via +one of the debug connectors, with appropriate software to be +master/slave/etc to correspond with the DUT. All (most) communication +lines between the two boards are tapped to a 10 pin connector matching +cheap FX2based logic analysers, allowing automatic tests to be written +that use sigrok to check that the signals on the wire match expectations. + |