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authorjaseg <git@jaseg.net>2018-07-17 15:43:26 +0200
committerjaseg <git@jaseg.net>2018-07-17 15:43:26 +0200
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downloadolsndot-6df66b77ba5b27bce5630694742f2dac57b8d3eb.tar.gz
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-This is a board designed to receive nucleo64 (and maybe 32) boards
-to be test TARGETS. The stm32l1 on _this_ board is reprogrammed via
-one of the debug connectors, with appropriate software to be
-master/slave/etc to correspond with the DUT. All (most) communication
-lines between the two boards are tapped to a 10 pin connector matching
-cheap FX2based logic analysers, allowing automatic tests to be written
-that use sigrok to check that the signals on the wire match expectations.
-
-
-Notes on assembly hw1-a:
-* 16Mhz crystal, 15pf load caps, and 3k7 i2c pullups
- (why don't I have 4k7 0603 resistors lying around? who knows!)
-* A power LED wouldn't hurt.
-* Adding a red/green user led wouldn't hurt for test pass/fail, even though
- it's meant to be autotest
-* maybe a fet to turn on/off the i2c pull ups programatically?
- (maybe just a single jumper? is there really any need for individual control
- of the pullups?)
-* move stlink connector 90° or just down and tuck it in, so we can pull the
- edge in. It overlaps the buttons on the nucleos, and requires longer
- pins than necessary otherwise.
-* Add some ground pads for test points, just in general. Test points good,
- more test points better.