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| author | jaseg <git@jaseg.net> | 2018-04-27 09:37:00 +0200 |
|---|---|---|
| committer | jaseg <git@jaseg.net> | 2018-04-27 09:37:00 +0200 |
| commit | e0eb2d53a9d93ed3e968f9d40b89df970045dfe1 (patch) | |
| tree | c81a8c9eab840790bed87f862cd1edbcff20d09e /firmware | |
| parent | a5f7fd8d2946fa6830deff1e6784e8b2be7cbb1c (diff) | |
| download | olsndot-e0eb2d53a9d93ed3e968f9d40b89df970045dfe1.tar.gz olsndot-e0eb2d53a9d93ed3e968f9d40b89df970045dfe1.tar.bz2 olsndot-e0eb2d53a9d93ed3e968f9d40b89df970045dfe1.zip | |
firmware: Small comment update
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/main.c b/firmware/main.c index 81ae15f..ec56767 100644 --- a/firmware/main.c +++ b/firmware/main.c @@ -176,7 +176,7 @@ int main(void) { /* Configure TIM1 for display strobe generation */ TIM1->CR1 = TIM_CR1_ARPE; - TIM1->PSC = 0; /* Prescale by 2, resulting in a 15MHz timer frequency and 66.7ns timer step size. */ + TIM1->PSC = 0; /* Do not prescale, resulting in a 30MHz timer frequency and 33.3ns timer step size. */ /* CH2 - clear/!MR, CH3 - strobe/STCP */ TIM1->CCMR2 = (6<<TIM_CCMR2_OC3M_Pos) | TIM_CCMR2_OC3PE | (6<<TIM_CCMR2_OC4M_Pos); TIM1->CCER |= TIM_CCER_CC3E | TIM_CCER_CC3NE | TIM_CCER_CC3P | TIM_CCER_CC3NP | TIM_CCER_CC4E; |