basic timer interleaving works

3 files changed, 32 insertions, 131 deletions

diff --git a/Makefile b/Makefile
index ea9ee6b..4cf97a7 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,4 @@
-# Megumin LED display firmware
+# MoaRGB RGB COB controller
 # Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
 # 
 # This program is free software: you can redistribute it and/or modify
@@ -18,6 +18,7 @@ CUBE_PATH 		?= $(wildcard ~)/resource/STM32CubeF1
 CMSIS_PATH 		?= $(CUBE_PATH)/Drivers/CMSIS
 CMSIS_DEV_PATH  ?= $(CMSIS_PATH)/Device/ST/STM32F1xx
 HAL_PATH   		?= $(CUBE_PATH)/Drivers/STM32F1xx_HAL_Driver
+USBD_PATH   	?= $(CUBE_PATH)/Middlewares/ST/STM32_USB_Device_Library
 
 CC      := arm-none-eabi-gcc
 LD      := arm-none-eabi-ld
diff --git a/main.c b/main.c
index 6b10c73..c1f2f41 100644
--- a/main.c
+++ b/main.c
@@ -17,14 +17,6 @@
 
 #include "global.h"
 
-#define RTC_INITIALIZED_REGISTER_HIGH BKP->DR1
-#define RTC_INITIALIZED_REGISTER_LOW BKP->DR2
-#define REBOOT_REGISTER BKP->DR3
-
-#define DAY_SECONDS (24*3600)
-
-void RTC_IRQHandler(void);
-
 uint32_t pcg32_random_r() {
     // *Really* minimal PCG32 code / (c) 2014 M.E. O'Neill / pcg-random.org
     // Licensed under Apache License 2.0 (NO WARRANTY, etc. see website)
@@ -39,64 +31,6 @@ uint32_t pcg32_random_r() {
     return (xorshifted >> rot) | (xorshifted << ((-rot) & 31));
 }
 
-unsigned char dumb_random() {
-    static unsigned char x=0x66, a=0x05, b=0xe3, c=0xbc;
-    x++; //x is incremented every round and is not affected by any other variable
-    a = (a ^ c ^ x); //note the mix of addition and XOR
-    b = (b + a); //And the use of very few instructions
-    c = (((c + (b >> 1)) ^ a)); // the AES S-Box Operation ensures an even distributon of entropy
-    return (c);
-}
-
-void rtc_write(volatile uint32_t *reg, uint32_t val) {
-    while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
-    RTC->CRL |= RTC_CRL_CNF;
-
-    reg[0] = val>>16;
-    reg[1] = val&0xffff;
-
-    RTC->CRL &= ~RTC_CRL_CNF;
-    while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
-}
-
-void rtc_alarm_reset(void) {
-    RTC->CRL &= ~RTC_CRL_ALRF;
-}
-
-void rtc_init(void) {
-    RTC->CRH = RTC_CRH_ALRIE;
-
-    /* Cold boot config */
-    if (((RTC_INITIALIZED_REGISTER_HIGH<<16) | RTC_INITIALIZED_REGISTER_LOW) != COMPILE_TIME) {
-        /* RTC clock config */
-        RCC->BDCR = RCC_BDCR_RTCEN | (1<<RCC_BDCR_RTCSEL_Pos) | RCC_BDCR_LSEON;
-        while (!(RCC->BDCR & RCC_BDCR_LSERDY)) ;
-
-        rtc_write(&RTC->PRLH, 32768-1);
-        rtc_write(&RTC->CNTH, COMPILE_TIME);
-        RTC_INITIALIZED_REGISTER_HIGH = COMPILE_TIME>>16;
-        RTC_INITIALIZED_REGISTER_LOW = COMPILE_TIME&0xffff;
-        REBOOT_REGISTER  = 0;
-    }
-
-    /* Synchronize RTC registers from backup domain */
-    RTC->CRL &= ~RTC_CRL_RSF;
-}
-
-void rtc_set_alarm_sec(uint32_t value) {
-    rtc_write(&RTC->ALRH, value);
-}
-
-uint32_t rtc_time(void) {
-    /* Wait for register synchronization after bootup */
-    while (!(RTC->CRL & RTC_CRL_RSF)) ;
-    return RTC->CNTH<<16 | RTC->CNTL;
-}
-
-void rtc_set_alarm_rel_sec(uint32_t value) {
-    rtc_set_alarm_sec(rtc_time() + value);
-}
-
 int main(void){
     /* We're starting out from HSI@8MHz */
     SystemCoreClockUpdate();
@@ -105,82 +39,46 @@ int main(void){
         asm volatile ("nop");
 
     /* Turn on lots of neat things */
-    RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPBEN;
-    RCC->APB1ENR |= RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN;
-    PWR->CR = PWR_CR_DBP;
+    RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
+    RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_TIM4EN;
 
     GPIOC->CRH |=
           (0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
-    GPIOB->CRH =
-          (0<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos); /* PB8 - MOSFET */
+    GPIOB->CRL |=
+          (2<<GPIO_CRL_CNF5_Pos) | (2<<GPIO_CRL_MODE5_Pos); /* PB5 - TIM3_CH2 */
+    AFIO->MAPR |= (2 << AFIO_MAPR_TIM3_REMAP_Pos); /* Map TIM3_CH2 to PB5 */
+    GPIOB->CRH |=
+          (2<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos)  /* PB8 - TIM4_CH3 */
+        | (2<<GPIO_CRH_CNF9_Pos) | (2<<GPIO_CRH_MODE9_Pos); /* PB9 - TIM4_CH4 */
     GPIOC->ODR |= 1<<13; /* LED */
-    GPIOB->ODR &= ~(1<<8); /* MOSFET */
-
-    rtc_init();
-    rtc_alarm_reset();
-    NVIC_ClearPendingIRQ(RTC_IRQn);
-    //NVIC_EnableIRQ(RTC_IRQn);
-    //NVIC_SetPriority(RTC_IRQn, 1);
 
-    rtc_set_alarm_rel_sec(1);
+    TIM3->SMCR = (3<<TIM_SMCR_TS_Pos) | (6 << TIM_SMCR_SMS_Pos);
+    TIM4->CR2 = (4<<TIM_CR2_MMS_Pos);
 
-    if (!(PWR->CSR & PWR_CSR_WUF)) /* This reset wasn't caused by the RTC alarm */
-        REBOOT_REGISTER++;
+    int period = 0xffff;
+    int thr[3] = {20000, 30000};
 
-    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
-    //SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk);
-    //PWR->CR &= (~PWR_CR_PDDS) & (~PWR_CR_LPDS);
-    while (42) {
-        RTC_IRQHandler();
-        PWR->CR |= PWR_CR_CWUF; /* This has 2 cycles latency, thus the NOPs */
-        asm volatile ("nop");
-        asm volatile ("nop");
-        asm volatile ("wfe");
-    }
-    //while (42)
-    //    asm volatile ("wfi");
-}
+    int overlap = 1000;
 
-void RTC_IRQHandler(void) {
-    rtc_alarm_reset();
-    rtc_set_alarm_rel_sec(1);
-
-    uint32_t now = rtc_time();
-    bool switch_on = false;
-    if (REBOOT_REGISTER > 1) { /* We have rebooted since initial bring-up */
-        /* Give status indication and active output as fail-safe */
-        if ((now&3) == 0) {
-            GPIOC->ODR &= ~(1<<13);
-            for (int i=0; i<5000; i++)
-                asm volatile ("nop");
-            GPIOC->ODR |= 1<<13;
-        }
-
-        switch_on = true;
-
-    } else {
-        switch_on = (now >= TARGET_DATE - (DAY_SECONDS*24) && now < TARGET_DATE);
-    }
-
-    if (switch_on && (now/2) % 3 == 0) {
-        GPIOB->ODR |= 1<<8;
+    TIM4->CCR3 = thr[0];
+    TIM4->CCR4 = thr[1];
+    TIM4->CCR1 = thr[0];
+    TIM3->CCR2 = thr[1] - thr[0];
+    TIM3->ARR = 0xfffe;
+    TIM4->ARR = 0xffff;
 
-        /* Go to sleep mode to keep GPIO active */
-        PWR->CR &= ~PWR_CR_PDDS;
-        SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); /* Use deep sleep mode */
+    TIM3->CCER = TIM_CCER_CC2E;
+    TIM3->CCMR1 = (0<<TIM_CCMR1_CC2S_Pos) | TIM_CCMR1_OC2PE | (6<<TIM_CCMR1_OC2M_Pos);
+    TIM4->CCER = TIM_CCER_CC3E | TIM_CCER_CC4E | TIM_CCER_CC1E | TIM_CCER_CC3P | TIM_CCER_CC4P;
+    TIM4->CCMR1 = (0<<TIM_CCMR1_CC1S_Pos) | TIM_CCMR1_OC1PE | (7<<TIM_CCMR1_OC1M_Pos);
+    TIM4->CCMR2 = (0<<TIM_CCMR2_CC4S_Pos) | TIM_CCMR2_OC4PE | (6<<TIM_CCMR2_OC4M_Pos) \
+                | (0<<TIM_CCMR2_CC3S_Pos) | TIM_CCMR2_OC3PE | (7<<TIM_CCMR2_OC3M_Pos);
 
-    } else {
-        GPIOB->ODR &= ~(1<<8);
+    TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_OPM;
+    TIM4->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN;
 
-        /* Go to standby mode to reduce power consumption */
-        PWR->CR = PWR_CR_PDDS;
-        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Use deep sleep mode */
+    for (;;) {
     }
-
-    GPIOC->ODR &= ~(1<<13);
-    for (int i=0; i<5000; i++)
-        asm volatile ("nop");
-    GPIOC->ODR |= 1<<13;
 }
 
 void gdb_dump(void) {
diff --git a/openocd.cfg b/openocd.cfg
index ba05b1e..3771d00 100644
--- a/openocd.cfg
+++ b/openocd.cfg
@@ -1,6 +1,8 @@
 telnet_port 4444
 gdb_port 3333
 
+set CPUTAPID 0x2ba01477
+
 source [find interface/stlink-v2.cfg]
 #hla_serial "000000000001"
 transport select hla_swd