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authorjaseg <git@jaseg.net>2019-07-07 12:49:25 +0900
committerjaseg <git@jaseg.net>2019-07-07 12:49:25 +0900
commit448bea3698927f7c975c79b3810a72d8c49b8f61 (patch)
treeff819c468370adee1e63eb196621aa52b60b2f47
parent8387226298732683e8d95b330fbc741b400436f9 (diff)
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Foo
-rw-r--r--main.c76
1 files changed, 48 insertions, 28 deletions
diff --git a/main.c b/main.c
index 7fd062b..ffd4c22 100644
--- a/main.c
+++ b/main.c
@@ -57,18 +57,16 @@ void rtc_write(volatile uint32_t *reg, uint32_t val) {
while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
}
-void rtc_bus_sync(void) {
- RTC->CRL &= ~RTC_CRL_RSF;
- while (!(RTC->CRL & RTC_CRL_RSF)) ;
-}
-
void rtc_alarm_reset(void) {
RTC->CRL &= ~RTC_CRL_ALRF;
}
void rtc_init(void) {
- RTC->CRH = 0;
+ RTC->CRH = RTC_CRH_ALRIE;
+
+ /* Cold boot config */
if (((RTC_INITIALIZED_REGISTER_HIGH<<16) | RTC_INITIALIZED_REGISTER_LOW) != COMPILE_TIME) {
+ /* RTC clock config */
RCC->BDCR = RCC_BDCR_RTCEN | (1<<RCC_BDCR_RTCSEL_Pos) | RCC_BDCR_LSEON;
while (!(RCC->BDCR & RCC_BDCR_LSERDY)) ;
@@ -78,7 +76,9 @@ void rtc_init(void) {
RTC_INITIALIZED_REGISTER_LOW = COMPILE_TIME&0xffff;
REBOOT_REGISTER = 0;
}
- rtc_bus_sync();
+
+ /* Synchronize RTC registers from backup domain */
+ RTC->CRL &= ~RTC_CRL_RSF;
}
void rtc_set_alarm_sec(uint32_t value) {
@@ -86,6 +86,8 @@ void rtc_set_alarm_sec(uint32_t value) {
}
uint32_t rtc_time(void) {
+ /* Wait for register synchronization after bootup */
+ while (!(RTC->CRL & RTC_CRL_RSF)) ;
return RTC->CNTH<<16 | RTC->CNTL;
}
@@ -96,27 +98,46 @@ void rtc_set_alarm_rel_sec(uint32_t value) {
int main(void){
/* We're starting out from HSI@8MHz */
SystemCoreClockUpdate();
- SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & SCB_SCR_SLEEPDEEP_Msk; /* Disable for now */
+ SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk); /* Disable for now */
for (int i=0; i<50000; i++)
asm volatile ("nop");
/* Turn on lots of neat things */
- RCC->APB2ENR |= RCC_APB2ENR_IOPCEN;
+ RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPBEN;
RCC->APB1ENR |= RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN;
PWR->CR = PWR_CR_DBP;
GPIOC->CRH |=
- (0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos)| /* PC13 - LED */
- (0<<GPIO_CRH_CNF14_Pos) | (2<<GPIO_CRH_MODE14_Pos); /* PC14 - MOSFET */
- GPIOC->ODR |= 1<<13;
- GPIOC->ODR &= ~(1<<14);
+ (0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
+ GPIOB->CRH |=
+ (0<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos); /* PB8 - MOSFET */
+ GPIOC->ODR |= 1<<13; /* LED */
+ GPIOB->ODR &= ~(1<<8); /* MOSFET */
rtc_init();
rtc_alarm_reset();
- rtc_set_alarm_rel_sec(0);
+ //NVIC_ClearPendingIRQ(RTC_IRQn);
+ NVIC_EnableIRQ(RTC_IRQn);
+ NVIC_SetPriority(RTC_IRQn, 1);
+
+ rtc_set_alarm_rel_sec(1);
+
+ //if (!(PWR->CSR & PWR_CSR_WUF)) /* This reset wasn't caused by the RTC alarm */
+ REBOOT_REGISTER++;
+
+ //SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+ //SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk);
+ //PWR->CR &= (~PWR_CR_PDDS) & (~PWR_CR_LPDS);
+ //PWR->CR |= PWR_CR_CWUF; /* This has 2 cycles latency, thus the NOPs */
+ //asm volatile ("nop");
+ //asm volatile ("nop");
+ while (42)
+ asm volatile ("wfi");
+}
- if (!(PWR->CSR & PWR_CSR_WUF)) /* This reset wasn't caused by the RTC alarm */
- REBOOT_REGISTER++;
+void RTC_IRQHandler(void) {
+ rtc_alarm_reset();
+ rtc_set_alarm_rel_sec(1);
uint32_t now = rtc_time();
bool switch_on = false;
@@ -135,26 +156,25 @@ int main(void){
switch_on = (now >= TARGET_DATE - (DAY_SECONDS*24) && now < TARGET_DATE);
}
- if (switch_on && now/300 % 24 == 0) {
- GPIOC->ODR |= 1<<14;
+ if (switch_on && (now/2) % 3 == 0) {
+ GPIOB->ODR |= 1<<8;
/* Go to sleep mode to keep GPIO active */
- PWR->CR &= ~PWR_CR_PDDS;
- SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); /* Use deep sleep mode */
+ //PWR->CR &= ~PWR_CR_PDDS;
+ //SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); /* Use deep sleep mode */
} else {
- GPIOC->ODR &= ~(1<<14);
+ GPIOB->ODR &= ~(1<<8);
/* Go to standby mode to reduce power consumption */
- PWR->CR = PWR_CR_PDDS;
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Use deep sleep mode */
+ //PWR->CR = PWR_CR_PDDS;
+ //SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Use deep sleep mode */
}
- PWR->CR |= PWR_CR_CWUF; /* This has 2 cycles latency, thus the NOPs */
- asm volatile ("nop");
- asm volatile ("nop");
- asm volatile ("wfe");
- return 42;
+ GPIOC->ODR &= ~(1<<13);
+ for (int i=0; i<5000; i++)
+ asm volatile ("nop");
+ GPIOC->ODR |= 1<<13;
}
void gdb_dump(void) {