diff options
Diffstat (limited to 'midi-dials/build/stm32f0xx_hal_cortex.lst')
| -rw-r--r-- | midi-dials/build/stm32f0xx_hal_cortex.lst | 174 |
1 files changed, 87 insertions, 87 deletions
diff --git a/midi-dials/build/stm32f0xx_hal_cortex.lst b/midi-dials/build/stm32f0xx_hal_cortex.lst index 114b6a1..4017aae 100644 --- a/midi-dials/build/stm32f0xx_hal_cortex.lst +++ b/midi-dials/build/stm32f0xx_hal_cortex.lst @@ -1,4 +1,4 @@ -ARM GAS /tmp/cceoVgjg.s page 1 +ARM GAS /tmp/ccwGqVnP.s page 1 1 .cpu cortex-m0 @@ -58,7 +58,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() 33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** - ARM GAS /tmp/cceoVgjg.s page 2 + ARM GAS /tmp/ccwGqVnP.s page 2 34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** -@- Negative value of IRQn_Type are not allowed. @@ -118,7 +118,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 88:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 89:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX 90:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief CORTEX CORTEX HAL module driver - ARM GAS /tmp/cceoVgjg.s page 3 + ARM GAS /tmp/ccwGqVnP.s page 3 91:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @{ @@ -178,7 +178,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 33 .cfi_def_cfa_offset 16 34 .cfi_offset 4, -16 35 .cfi_offset 5, -12 - ARM GAS /tmp/cceoVgjg.s page 4 + ARM GAS /tmp/ccwGqVnP.s page 4 36 .cfi_offset 6, -8 @@ -238,7 +238,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 49:Drivers/CMSIS/Include/core_cm0.h **** 50:Drivers/CMSIS/Include/core_cm0.h **** \li Advisory Rule 19.7, Function-like macro defined.<br> 51:Drivers/CMSIS/Include/core_cm0.h **** Function-like macros are used to allow more efficient code. - ARM GAS /tmp/cceoVgjg.s page 5 + ARM GAS /tmp/ccwGqVnP.s page 5 52:Drivers/CMSIS/Include/core_cm0.h **** */ @@ -298,7 +298,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 106:Drivers/CMSIS/Include/core_cm0.h **** #endif 107:Drivers/CMSIS/Include/core_cm0.h **** 108:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __CSMC__ ) - ARM GAS /tmp/cceoVgjg.s page 6 + ARM GAS /tmp/ccwGqVnP.s page 6 109:Drivers/CMSIS/Include/core_cm0.h **** #if ( __CSMC__ & 0x400U) @@ -358,7 +358,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 163:Drivers/CMSIS/Include/core_cm0.h **** #endif 164:Drivers/CMSIS/Include/core_cm0.h **** #define __O volatile /*!< Defines 'write only' permissions */ 165:Drivers/CMSIS/Include/core_cm0.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ - ARM GAS /tmp/cceoVgjg.s page 7 + ARM GAS /tmp/ccwGqVnP.s page 7 166:Drivers/CMSIS/Include/core_cm0.h **** @@ -418,7 +418,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 220:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 221:Drivers/CMSIS/Include/core_cm0.h **** 222:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_V_Pos 28U /*!< APSR - ARM GAS /tmp/cceoVgjg.s page 8 + ARM GAS /tmp/ccwGqVnP.s page 8 223:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR @@ -478,7 +478,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 277:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 278:Drivers/CMSIS/Include/core_cm0.h **** 279:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_ISR_Pos 0U /*!< xPSR - ARM GAS /tmp/cceoVgjg.s page 9 + ARM GAS /tmp/ccwGqVnP.s page 9 280:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR @@ -538,7 +538,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 334:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions for the System Control Block Registers 335:Drivers/CMSIS/Include/core_cm0.h **** @{ 336:Drivers/CMSIS/Include/core_cm0.h **** */ - ARM GAS /tmp/cceoVgjg.s page 10 + ARM GAS /tmp/ccwGqVnP.s page 10 337:Drivers/CMSIS/Include/core_cm0.h **** @@ -598,7 +598,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 391:Drivers/CMSIS/Include/core_cm0.h **** 392:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 393:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB - ARM GAS /tmp/cceoVgjg.s page 11 + ARM GAS /tmp/ccwGqVnP.s page 11 394:Drivers/CMSIS/Include/core_cm0.h **** @@ -658,7 +658,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 448:Drivers/CMSIS/Include/core_cm0.h **** typedef struct 449:Drivers/CMSIS/Include/core_cm0.h **** { 450:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis - ARM GAS /tmp/cceoVgjg.s page 12 + ARM GAS /tmp/ccwGqVnP.s page 12 451:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ @@ -718,7 +718,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 505:Drivers/CMSIS/Include/core_cm0.h **** */ 506:Drivers/CMSIS/Include/core_cm0.h **** 507:Drivers/CMSIS/Include/core_cm0.h **** /** - ARM GAS /tmp/cceoVgjg.s page 13 + ARM GAS /tmp/ccwGqVnP.s page 13 508:Drivers/CMSIS/Include/core_cm0.h **** \brief Mask and shift a bit field value for use in a register bit range. @@ -778,7 +778,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 562:Drivers/CMSIS/Include/core_cm0.h **** /** 563:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_Core_FunctionInterface 564:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions - ARM GAS /tmp/cceoVgjg.s page 14 + ARM GAS /tmp/ccwGqVnP.s page 14 565:Drivers/CMSIS/Include/core_cm0.h **** \brief Functions that manage interrupts and exceptions via the NVIC. @@ -838,7 +838,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 619:Drivers/CMSIS/Include/core_cm0.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 620:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. 621:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. - ARM GAS /tmp/cceoVgjg.s page 15 + ARM GAS /tmp/ccwGqVnP.s page 15 622:Drivers/CMSIS/Include/core_cm0.h **** */ @@ -898,7 +898,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 676:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. 677:Drivers/CMSIS/Include/core_cm0.h **** */ 678:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) - ARM GAS /tmp/cceoVgjg.s page 16 + ARM GAS /tmp/ccwGqVnP.s page 16 679:Drivers/CMSIS/Include/core_cm0.h **** { @@ -958,7 +958,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 42 .loc 2 732 0 43 0002 0028 cmp r0, #0 44 0004 11DB blt .L2 - ARM GAS /tmp/cceoVgjg.s page 17 + ARM GAS /tmp/ccwGqVnP.s page 17 733:Drivers/CMSIS/Include/core_cm0.h **** { @@ -1018,7 +1018,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 87 0038 094A ldr r2, .L4+4 88 .LVL7: 89 003a 9446 mov ip, r2 - ARM GAS /tmp/cceoVgjg.s page 18 + ARM GAS /tmp/ccwGqVnP.s page 18 90 003c 6344 add r3, r3, ip @@ -1078,7 +1078,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 132 .cfi_startproc 133 @ args = 0, pretend = 0, frame = 0 134 @ frame_needed = 0, uses_anonymous_args = 0 - ARM GAS /tmp/cceoVgjg.s page 19 + ARM GAS /tmp/ccwGqVnP.s page 19 135 @ link register save eliminated. @@ -1138,7 +1138,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 169:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 174 .loc 1 169 0 175 .cfi_startproc - ARM GAS /tmp/cceoVgjg.s page 20 + ARM GAS /tmp/ccwGqVnP.s page 20 176 @ args = 0, pretend = 0, frame = 0 @@ -1198,7 +1198,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ - ARM GAS /tmp/cceoVgjg.s page 21 + ARM GAS /tmp/ccwGqVnP.s page 21 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin @@ -1258,7 +1258,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop - ARM GAS /tmp/cceoVgjg.s page 22 + ARM GAS /tmp/ccwGqVnP.s page 22 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add @@ -1318,7 +1318,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. - ARM GAS /tmp/cceoVgjg.s page 23 + ARM GAS /tmp/ccwGqVnP.s page 23 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value @@ -1378,7 +1378,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) - ARM GAS /tmp/cceoVgjg.s page 24 + ARM GAS /tmp/ccwGqVnP.s page 24 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { @@ -1438,7 +1438,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) - ARM GAS /tmp/cceoVgjg.s page 25 + ARM GAS /tmp/ccwGqVnP.s page 25 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { @@ -1498,7 +1498,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** - ARM GAS /tmp/cceoVgjg.s page 26 + ARM GAS /tmp/ccwGqVnP.s page 26 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); @@ -1558,7 +1558,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** - ARM GAS /tmp/cceoVgjg.s page 27 + ARM GAS /tmp/ccwGqVnP.s page 27 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** @@ -1618,7 +1618,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - ARM GAS /tmp/cceoVgjg.s page 28 + ARM GAS /tmp/ccwGqVnP.s page 28 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** @@ -1678,7 +1678,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ - ARM GAS /tmp/cceoVgjg.s page 29 + ARM GAS /tmp/ccwGqVnP.s page 29 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) @@ -1738,7 +1738,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); - ARM GAS /tmp/cceoVgjg.s page 30 + ARM GAS /tmp/ccwGqVnP.s page 30 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } @@ -1798,7 +1798,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** - ARM GAS /tmp/cceoVgjg.s page 31 + ARM GAS /tmp/ccwGqVnP.s page 31 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) @@ -1858,7 +1858,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI - ARM GAS /tmp/cceoVgjg.s page 32 + ARM GAS /tmp/ccwGqVnP.s page 32 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; @@ -1918,7 +1918,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - ARM GAS /tmp/cceoVgjg.s page 33 + ARM GAS /tmp/ccwGqVnP.s page 33 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure @@ -1978,7 +1978,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else - ARM GAS /tmp/cceoVgjg.s page 34 + ARM GAS /tmp/ccwGqVnP.s page 34 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; @@ -2038,7 +2038,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** - ARM GAS /tmp/cceoVgjg.s page 35 + ARM GAS /tmp/ccwGqVnP.s page 35 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation @@ -2098,7 +2098,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 204 .LBE41: 205 .LBE40: 206 .LBB42: - ARM GAS /tmp/cceoVgjg.s page 36 + ARM GAS /tmp/ccwGqVnP.s page 36 207 .LBB43: @@ -2158,7 +2158,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 249 .LBB52: 250 .LBB53: 251 .loc 3 879 0 - ARM GAS /tmp/cceoVgjg.s page 37 + ARM GAS /tmp/ccwGqVnP.s page 37 252 .syntax divided @@ -2218,7 +2218,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 787:Drivers/CMSIS/Include/core_cm0.h **** 788:Drivers/CMSIS/Include/core_cm0.h **** return ( 789:Drivers/CMSIS/Include/core_cm0.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits - ARM GAS /tmp/cceoVgjg.s page 38 + ARM GAS /tmp/ccwGqVnP.s page 38 790:Drivers/CMSIS/Include/core_cm0.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) @@ -2278,7 +2278,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 844:Drivers/CMSIS/Include/core_cm0.h **** */ 845:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 846:Drivers/CMSIS/Include/core_cm0.h **** { - ARM GAS /tmp/cceoVgjg.s page 39 + ARM GAS /tmp/ccwGqVnP.s page 39 847:Drivers/CMSIS/Include/core_cm0.h **** uint32_t *vectors = (uint32_t *)0x0U; @@ -2338,7 +2338,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 295 .align 1 296 .global HAL_SYSTICK_Config 297 .syntax unified - ARM GAS /tmp/cceoVgjg.s page 40 + ARM GAS /tmp/ccwGqVnP.s page 40 298 .code 16 @@ -2398,7 +2398,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 895:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of CMSIS_Core_FpuFunctions */ 896:Drivers/CMSIS/Include/core_cm0.h **** 897:Drivers/CMSIS/Include/core_cm0.h **** - ARM GAS /tmp/cceoVgjg.s page 41 + ARM GAS /tmp/ccwGqVnP.s page 41 898:Drivers/CMSIS/Include/core_cm0.h **** @@ -2458,7 +2458,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 335 .LBE59: 336 .LBE58: 928:Drivers/CMSIS/Include/core_cm0.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int - ARM GAS /tmp/cceoVgjg.s page 42 + ARM GAS /tmp/ccwGqVnP.s page 42 929:Drivers/CMSIS/Include/core_cm0.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val @@ -2518,7 +2518,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 200:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 201:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 202:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - ARM GAS /tmp/cceoVgjg.s page 43 + ARM GAS /tmp/ccwGqVnP.s page 43 203:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Cortex control functions @@ -2578,7 +2578,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 409 .LBE65: 410 .LBE64: 228:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ - ARM GAS /tmp/cceoVgjg.s page 44 + ARM GAS /tmp/ccwGqVnP.s page 44 229:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** return NVIC_GetPriority(IRQn); @@ -2638,7 +2638,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 233:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. 234:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number 235:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration - ARM GAS /tmp/cceoVgjg.s page 45 + ARM GAS /tmp/ccwGqVnP.s page 45 236:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI @@ -2698,7 +2698,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 504 HAL_NVIC_GetPendingIRQ: 505 .LFB47: 247:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** - ARM GAS /tmp/cceoVgjg.s page 46 + ARM GAS /tmp/ccwGqVnP.s page 46 248:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @@ -2758,7 +2758,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 540 0018 0020 movs r0, #0 541 .LVL38: 542 .LBE72: - ARM GAS /tmp/cceoVgjg.s page 47 + ARM GAS /tmp/ccwGqVnP.s page 47 543 .LBE73: @@ -2818,7 +2818,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 586 .LBE75: 587 .LBE74: 275:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ - ARM GAS /tmp/cceoVgjg.s page 48 + ARM GAS /tmp/ccwGqVnP.s page 48 276:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); @@ -2878,7 +2878,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 619 0006 1368 ldr r3, [r2] 620 0008 0421 movs r1, #4 621 000a 8B43 bics r3, r1 - ARM GAS /tmp/cceoVgjg.s page 49 + ARM GAS /tmp/ccwGqVnP.s page 49 622 000c 1360 str r3, [r2] @@ -2938,7 +2938,7 @@ ARM GAS /tmp/cceoVgjg.s page 1 321:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 322:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 657 .loc 1 322 0 - ARM GAS /tmp/cceoVgjg.s page 50 + ARM GAS /tmp/ccwGqVnP.s page 50 658 @ sp needed @@ -2977,48 +2977,48 @@ ARM GAS /tmp/cceoVgjg.s page 1 691 .text 692 .Letext0: 693 .file 4 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h" - 694 .file 5 "/home/janhenrik/programme/gcc-arm-none-eabi-7-2018-q2-update/arm-none-eabi/include/machin - 695 .file 6 "/home/janhenrik/programme/gcc-arm-none-eabi-7-2018-q2-update/arm-none-eabi/include/sys/_s + 694 .file 5 "/usr/include/newlib/machine/_default_types.h" + 695 .file 6 "/usr/include/newlib/sys/_stdint.h" 696 .file 7 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" 697 .file 8 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h" - ARM GAS /tmp/cceoVgjg.s page 51 + ARM GAS /tmp/ccwGqVnP.s page 51 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f0xx_hal_cortex.c - /tmp/cceoVgjg.s:16 .text.HAL_NVIC_SetPriority:0000000000000000 $t - /tmp/cceoVgjg.s:23 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority - /tmp/cceoVgjg.s:116 .text.HAL_NVIC_SetPriority:000000000000005c $d - /tmp/cceoVgjg.s:122 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t - /tmp/cceoVgjg.s:129 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ - /tmp/cceoVgjg.s:160 .text.HAL_NVIC_EnableIRQ:0000000000000014 $d - /tmp/cceoVgjg.s:165 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t - /tmp/cceoVgjg.s:172 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ - /tmp/cceoVgjg.s:227 .text.HAL_NVIC_DisableIRQ:000000000000001c $d - /tmp/cceoVgjg.s:232 .text.HAL_NVIC_SystemReset:0000000000000000 $t - /tmp/cceoVgjg.s:239 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset - /tmp/cceoVgjg.s:287 .text.HAL_NVIC_SystemReset:0000000000000014 $d - /tmp/cceoVgjg.s:295 .text.HAL_SYSTICK_Config:0000000000000000 $t - /tmp/cceoVgjg.s:302 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config - /tmp/cceoVgjg.s:366 .text.HAL_SYSTICK_Config:000000000000002c $d - /tmp/cceoVgjg.s:373 .text.HAL_NVIC_GetPriority:0000000000000000 $t - /tmp/cceoVgjg.s:380 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority - /tmp/cceoVgjg.s:446 .text.HAL_NVIC_GetPriority:0000000000000044 $d - /tmp/cceoVgjg.s:452 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t - /tmp/cceoVgjg.s:459 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ - /tmp/cceoVgjg.s:492 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d - /tmp/cceoVgjg.s:497 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t - /tmp/cceoVgjg.s:504 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ - /tmp/cceoVgjg.s:549 .text.HAL_NVIC_GetPendingIRQ:000000000000001c $d - /tmp/cceoVgjg.s:554 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t - /tmp/cceoVgjg.s:561 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ - /tmp/cceoVgjg.s:594 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d - /tmp/cceoVgjg.s:599 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t - /tmp/cceoVgjg.s:606 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig - /tmp/cceoVgjg.s:638 .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d - /tmp/cceoVgjg.s:643 .text.HAL_SYSTICK_Callback:0000000000000000 $t - /tmp/cceoVgjg.s:650 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback - /tmp/cceoVgjg.s:664 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t - /tmp/cceoVgjg.s:671 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler + /tmp/ccwGqVnP.s:16 .text.HAL_NVIC_SetPriority:0000000000000000 $t + /tmp/ccwGqVnP.s:23 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority + /tmp/ccwGqVnP.s:116 .text.HAL_NVIC_SetPriority:000000000000005c $d + /tmp/ccwGqVnP.s:122 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t + /tmp/ccwGqVnP.s:129 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ + /tmp/ccwGqVnP.s:160 .text.HAL_NVIC_EnableIRQ:0000000000000014 $d + /tmp/ccwGqVnP.s:165 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t + /tmp/ccwGqVnP.s:172 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ + /tmp/ccwGqVnP.s:227 .text.HAL_NVIC_DisableIRQ:000000000000001c $d + /tmp/ccwGqVnP.s:232 .text.HAL_NVIC_SystemReset:0000000000000000 $t + /tmp/ccwGqVnP.s:239 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset + /tmp/ccwGqVnP.s:287 .text.HAL_NVIC_SystemReset:0000000000000014 $d + /tmp/ccwGqVnP.s:295 .text.HAL_SYSTICK_Config:0000000000000000 $t + /tmp/ccwGqVnP.s:302 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config + /tmp/ccwGqVnP.s:366 .text.HAL_SYSTICK_Config:000000000000002c $d + /tmp/ccwGqVnP.s:373 .text.HAL_NVIC_GetPriority:0000000000000000 $t + /tmp/ccwGqVnP.s:380 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority + /tmp/ccwGqVnP.s:446 .text.HAL_NVIC_GetPriority:0000000000000044 $d + /tmp/ccwGqVnP.s:452 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t + /tmp/ccwGqVnP.s:459 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ + /tmp/ccwGqVnP.s:492 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d + /tmp/ccwGqVnP.s:497 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t + /tmp/ccwGqVnP.s:504 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ + /tmp/ccwGqVnP.s:549 .text.HAL_NVIC_GetPendingIRQ:000000000000001c $d + /tmp/ccwGqVnP.s:554 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t + /tmp/ccwGqVnP.s:561 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ + /tmp/ccwGqVnP.s:594 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d + /tmp/ccwGqVnP.s:599 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t + /tmp/ccwGqVnP.s:606 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig + /tmp/ccwGqVnP.s:638 .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d + /tmp/ccwGqVnP.s:643 .text.HAL_SYSTICK_Callback:0000000000000000 $t + /tmp/ccwGqVnP.s:650 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback + /tmp/ccwGqVnP.s:664 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t + /tmp/ccwGqVnP.s:671 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler NO UNDEFINED SYMBOLS |