summaryrefslogtreecommitdiff
path: root/pcb/edgerails/edgerails.pro
diff options
context:
space:
mode:
authorjaseg <git-bigdata-wsl-arch@jaseg.de>2020-05-03 19:53:02 +0200
committerjaseg <git-bigdata-wsl-arch@jaseg.de>2020-05-03 19:53:02 +0200
commit2628932a40d769d8d0180ba6fed1e7b9b2718982 (patch)
treeea485897653003d01cd16e2b506f69363928fafa /pcb/edgerails/edgerails.pro
parent972da3c0fd449dd6153edaf3c56e0c50d16b726b (diff)
downloadminikbd-2628932a40d769d8d0180ba6fed1e7b9b2718982.tar.gz
minikbd-2628932a40d769d8d0180ba6fed1e7b9b2718982.tar.bz2
minikbd-2628932a40d769d8d0180ba6fed1e7b9b2718982.zip
minkbd: repo restructure
Diffstat (limited to 'pcb/edgerails/edgerails.pro')
-rw-r--r--pcb/edgerails/edgerails.pro33
1 files changed, 33 insertions, 0 deletions
diff --git a/pcb/edgerails/edgerails.pro b/pcb/edgerails/edgerails.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/pcb/edgerails/edgerails.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]