master-thesis.git - Safety Reset: My master thesis on how to reset smart meters during a cyberwar through a signal encoded in the grid frequency

Age	Commit message (Expand)	Author	Files	Lines
2020-05-05	fw: Tie together all parts for an end-to-end demo	jaseg	7	-21/+79
2020-05-04	fw: add working reed-solomon encoder/decoder	jaseg	11	-435/+136
2020-04-29	MSP430 reflash working	jaseg	2	-26/+41
2020-04-20	Add fw simulator	jaseg	1	-1/+2
2020-04-17	fw simulator: WIP	jaseg	3	-22/+25
2020-04-01	Update thesis	jaseg	1	-1/+1
2020-03-21	Basic JTAG working	jaseg	8	-65/+146
2020-03-18	Fix firmware dsss decoding bug	jaseg	1	-1/+2
2020-03-18	Improve detector	jaseg	3	-25/+46
2020-03-18	Improve frequency measurement error detection	jaseg	1	-1/+1
2020-03-17	Debugging signal capture subsystem	jaseg	5	-4/+51
2020-03-16	Fix serial	jaseg	11	-40/+431
2020-03-15	Add end-to-end simulation	jaseg	4	-23/+96
2020-03-14	Fixup clock config	jaseg	2	-35/+86
2020-03-13	having problems with dma m2m mode	jaseg	2	-9/+19
2020-03-13	prettify linkmem	jaseg	1	-3/+10
2020-03-11	Start with integration of everything	jaseg	15	-82/+1680
2020-03-10	Crypto v2 draft working	jaseg	2	-36/+64
2020-03-09	WIP cryptographic design	jaseg	4	-3/+82
2020-03-09	Fix a bunch of compiler warnings	jaseg	2	-17/+17
2020-03-09	DSSS sequence matcher works	jaseg	1	-19/+2
2020-03-09	foo	jaseg	2	-25/+34
2020-03-09	demod wip	jaseg	2	-43/+162
2020-03-09	decoding WIP	jaseg	2	-18/+79
2020-03-06	Finish DSSS demodulation stage 1	jaseg	2	-44/+46
2020-03-06	Correlator seems to be working	jaseg	1	-12/+13
2020-03-06	WIP DSSS decoding	jaseg	1	-27/+34
2020-03-05	Working on DSSS demodulator sim	jaseg	3	-0/+225
2020-03-04	Fix frequency measurement simulation	jaseg	3	-15/+70
2020-03-03	working on testing	jaseg	1	-12/+12
2020-03-02	Finishing up freq meas	jaseg	7	-0/+794
2020-02-27	Add missing files	jaseg	9	-0/+620