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-rw-r--r--controller/fw/src/adc.c41
-rw-r--r--controller/fw/src/main.c80
2 files changed, 86 insertions, 35 deletions
diff --git a/controller/fw/src/adc.c b/controller/fw/src/adc.c
index fba2420..07431be 100644
--- a/controller/fw/src/adc.c
+++ b/controller/fw/src/adc.c
@@ -1,4 +1,6 @@
+#include <string.h>
+
#include <stm32f407xx.h>
#include <stm32f4_isr.h>
@@ -9,7 +11,6 @@ uint16_t adc_fft_buf[2][FMEAS_FFT_LEN];
volatile int adc_fft_buf_ready_idx = -1;
static DMA_TypeDef *const adc_dma = DMA2;
-static DMA_Stream_TypeDef *const mem_stream = DMA2_Stream1;
static DMA_Stream_TypeDef *const adc_stream = DMA2_Stream0;
static const int dma_adc_channel = 0;
static const int adc_channel = 10;
@@ -37,7 +38,7 @@ void adc_init() {
while (adc_stream->CR & DMA_SxCR_EN)
; /* wait for stream to become available */
adc_stream->NDTR = FMEAS_FFT_LEN/2;
- adc_stream->PAR = &(ADC1->DR);
+ adc_stream->PAR = (uint32_t) &(ADC1->DR);
adc_stream->M0AR = (uint32_t) (adc_fft_buf[0] + FMEAS_FFT_LEN/2);
adc_stream->M1AR = (uint32_t) (adc_fft_buf[1] + FMEAS_FFT_LEN/2);
adc_stream->CR = (dma_adc_channel<<DMA_SxCR_CHSEL_Pos) | DMA_SxCR_DBM | (1<<DMA_SxCR_MSIZE_Pos)
@@ -60,35 +61,39 @@ void adc_init() {
TIM1->ARR = 1000-1; /* 1ms period */
TIM1->CCR1 = 500-1;
TIM1->BDTR = TIM_BDTR_MOE;
+
+ /* DEBUG */
+ TIM1->DIER = TIM_DIER_CC1IE;
+ NVIC_EnableIRQ(TIM1_CC_IRQn);
+ NVIC_SetPriority(TIM1_CC_IRQn, 130);
+ /* END DEBUG */
+
TIM1->CR1 = TIM_CR1_CEN;
TIM1->EGR = TIM_EGR_UG;
}
+void TIM1_CC_IRQHandler(void) {
+ TIM1->SR &= ~TIM_SR_CC1IF;
+ static int foo=0;
+ foo++;
+ if (foo == 500) {
+ foo = 0;
+ GPIOA->ODR ^= 1<<6;
+ }
+}
+
void DMA2_Stream0_IRQHandler(void) {
uint8_t isr = (DMA2->LISR >> DMA_LISR_FEIF0_Pos) & 0x3f;
+ GPIOA->ODR ^= 1<<7;
+
if (isr & DMA_LISR_TCIF0) { /* Transfer complete */
/* Check we're done processing the old buffer */
if (adc_fft_buf_ready_idx != -1)
panic();
- /* Kickoff memory DMA into new buffer */
- if (mem_stream->CR & DMA_SxCR_EN)
- panic(); /* We should be long done by now. */
-
- adc_dma->LIFCR = 0x3d<<DMA_LISR_FEIF1_Pos;
- mem_stream->NDTR = FMEAS_FFT_LEN/2;
- int ct = !!(adc_stream->CR & DMA_SxCR_CT);
- /* back half of old buffer (that was just written) */
- mem_stream->PAR = (uint32_t)(adc_fft_buf[!ct] + FMEAS_FFT_LEN/2);
- /* front half of current buffer (whose back half is being written now) */
- mem_stream->M0AR = (uint32_t) (adc_fft_buf[ct] + 0);
-
- mem_stream->CR = (1<<DMA_SxCR_MSIZE_Pos) | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | DMA_SxCR_PINC
- | (0<<DMA_SxCR_PL_Pos) | (2<<DMA_SxCR_DIR_Pos);
- mem_stream->CR |= DMA_SxCR_EN;
-
/* Kickoff FFT */
+ int ct = !!(adc_stream->CR & DMA_SxCR_CT);
adc_fft_buf_ready_idx = !ct;
}
diff --git a/controller/fw/src/main.c b/controller/fw/src/main.c
index 4f2d67b..c03bcbb 100644
--- a/controller/fw/src/main.c
+++ b/controller/fw/src/main.c
@@ -2,6 +2,7 @@
#include <stdbool.h>
#include <stdint.h>
#include <assert.h>
+#include <string.h>
#include <stm32f407xx.h>
@@ -28,13 +29,19 @@ static void clock_setup(void)
#define PLL_M 8
/* Multiply by 336 -> 336 MHz VCO frequency */
#define PLL_N 336
- /* Divide by 2 -> 168 MHz (max freq for our chip) */
-#define PLL_P 2
+ /* Divide by 4 -> 84 MHz (max freq for our chip) */
+#define PLL_P 4
/* Aux clock for USB OTG, SDIO, RNG: divide VCO frequency (336 MHz) by 7 -> 48 MHz (required by USB OTG) */
#define PLL_Q 7
+ if (((RCC->CFGR & RCC_CFGR_SWS_Msk) >> RCC_CFGR_SW_Pos) != 0)
+ asm volatile ("bkpt");
+ if (RCC->CR & RCC_CR_HSEON)
+ asm volatile ("bkpt");
+
RCC->CR |= RCC_CR_HSEON;
- while(!(RCC->CR & RCC_CR_HSERDY));
+ while(!(RCC->CR & RCC_CR_HSERDY))
+ ;
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
@@ -46,19 +53,26 @@ static void clock_setup(void)
/* set AHB prescaler to /1 (CFGR:bits 7:4) */
RCC->CFGR |= (0 << RCC_CFGR_HPRE_Pos);
- /* set ABP1 prescaler to 4 */
- RCC->CFGR |= (5 << RCC_CFGR_PPRE1_Pos);
- /* set ABP2 prescaler to 2 */
- RCC->CFGR |= (0x4 << RCC_CFGR_PPRE2_Pos);
+ /* set ABP1 prescaler to 2 -> 42MHz */
+ RCC->CFGR |= (4 << RCC_CFGR_PPRE1_Pos);
+ /* set ABP2 prescaler to 1 -> 84MHz */
+ RCC->CFGR |= (0 << RCC_CFGR_PPRE2_Pos);
+ if (RCC->CR & RCC_CR_PLLON)
+ asm volatile ("bkpt");
/* Configure PLL */
static_assert(PLL_P % 2 == 0);
static_assert(PLL_P >= 2 && PLL_P <= 8);
static_assert(PLL_N >= 50 && PLL_N <= 432);
static_assert(PLL_M >= 2 && PLL_M <= 63);
static_assert(PLL_Q >= 2 && PLL_Q <= 15);
- RCC->PLLCFGR = (PLL_M<<RCC_PLLCFGR_PLLM_Pos)
- | (PLL_N << RCC_PLLCFGR_PLLM_Pos)
+ uint32_t old = RCC->PLLCFGR & ~(RCC_PLLCFGR_PLLM_Msk
+ | RCC_PLLCFGR_PLLN_Msk
+ | RCC_PLLCFGR_PLLP_Msk
+ | RCC_PLLCFGR_PLLQ_Msk
+ | RCC_PLLCFGR_PLLSRC);
+ RCC->PLLCFGR = old | (PLL_M<<RCC_PLLCFGR_PLLM_Pos)
+ | (PLL_N << RCC_PLLCFGR_PLLN_Pos)
| ((PLL_P/2 - 1) << RCC_PLLCFGR_PLLP_Pos)
| (PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
| RCC_PLLCFGR_PLLSRC; /* select HSE as PLL source */
@@ -71,7 +85,7 @@ static void clock_setup(void)
/* Configure Flash: enable prefetch, insn cache, data cache; set latency = 5 wait states
* See reference manual (RM0090), Section 3.5.1, Table 10 (p. 80)
*/
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | (5<<FLASH_ACR_LATENCY);
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | (5<<FLASH_ACR_LATENCY_Pos);
/* Select PLL as system clock source */
RCC->CFGR &= ~RCC_CFGR_SW_Msk;
@@ -84,6 +98,7 @@ static void clock_setup(void)
static void led_setup(void)
{
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
GPIOA->MODER |= (1<<GPIO_MODER_MODER6_Pos) | (1<<GPIO_MODER_MODER7_Pos);
}
@@ -148,25 +163,56 @@ static uint32_t debug_last_freq = 0;
int main(void)
{
+ /* DEBUG */
+ /* MCO2 */
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
+ GPIOC->MODER &= ~GPIO_MODER_MODER9_Msk;
+ GPIOC->MODER |= (2<<GPIO_MODER_MODER9_Pos);
+ GPIOC->AFR[1] &= ~GPIO_AFRH_AFSEL9_Msk;
+ GPIOC->OSPEEDR |= (3<<GPIO_OSPEEDR_OSPEED9_Pos); /* SCK */
+ RCC->CFGR |= (6<<RCC_CFGR_MCO2PRE_Pos) | (3<<RCC_CFGR_MCO2_Pos);
+ /* END DEBUG */
+
clock_setup();
led_setup();
+ /*
spi_flash_setup();
adc_init();
+ */
+ /* DEBUG */
+ /* TIM1 CC1 */
+ GPIOA->MODER &= ~GPIO_MODER_MODER8_Msk;
+ GPIOA->MODER |= (2<<GPIO_MODER_MODER8_Pos);
+ GPIOA->AFR[1] &= ~GPIO_AFRH_AFSEL8_Msk;
+ GPIOA->AFR[1] |= 1<<GPIO_AFRH_AFSEL8_Pos;
+ /* END DEBUG */
+
+ int cnt = 0;
while (23) {
+ if (cnt++ == 100000) {
+ cnt = 0;
+ GPIOA->ODR ^= 1<<6;
+ }
+
if (adc_fft_buf_ready_idx != -1) {
- /*
+ memcpy(adc_fft_buf[!adc_fft_buf_ready_idx], adc_fft_buf[adc_fft_buf_ready_idx] + FMEAS_FFT_LEN/2, sizeof(adc_fft_buf[0][0]) * FMEAS_FFT_LEN/2);
+
+#if 0
float out;
if (adc_buf_measure_freq(adc_fft_buf[adc_fft_buf_ready_idx], &out)) {
measurement_errors++;
- continue;
- }
+ debug_last_freq = -1;
- debug_last_freq = out;
+ } else {
+ debug_last_freq = out;
- dsss_demod_init(&demod_state);
- dsss_demod_step(&demod_state, out, freq_sample_ts);
- */
+ /*
+ dsss_demod_init(&demod_state);
+ dsss_demod_step(&demod_state, out, freq_sample_ts);
+ */
+ }
+#endif
freq_sample_ts++; /* TODO: also increase in case of freq measurement error? */
adc_fft_buf_ready_idx = -1;
generated by cgit (git 2.34.1) at 2024-11-24 04:46:52 +0000