.gitmodules


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[submodule "prototype/dbg-connect"]
	path = prototype/dbg-connect
	url = https://git.jaseg.de/dbg-connect.git
    branch = master

[submodule "prototype/fw/upstream/cmsis-core"]
	path = prototype/fw/upstream/cmsis-core
	url = https://github.com/STMicroelectronics/cmsis_core
    branch = master

[submodule "prototype/fw/upstream/cmsis-device-f3"]
	path = prototype/fw/upstream/cmsis-device-f3
	url = https://github.com/STMicroelectronics/cmsis_device_f3
    branch = master

[submodule "prototype/fw/upstream/tinyprintf"]
	path = prototype/fw/upstream/tinyprintf
	url = https://github.com/cjlano/tinyprintf
    branch = master

[submodule "prototype/fw/upstream/stm32square"]
	path = prototype/fw/upstream/stm32square
	url = https://gitlab.com/neinseg/stm32square
	branch = release
[submodule "prototype/fw/upstream/PyCortexMDebug"]
	path = prototype/fw/upstream/PyCortexMDebug
	url = https://github.com/bnahill/PyCortexMDebug