diff options
Diffstat (limited to 'prototype/mech_pcbs/stator_base_pcb/stator_base_pcb.kicad_pro')
| -rw-r--r-- | prototype/mech_pcbs/stator_base_pcb/stator_base_pcb.kicad_pro | 236 |
1 files changed, 229 insertions, 7 deletions
diff --git a/prototype/mech_pcbs/stator_base_pcb/stator_base_pcb.kicad_pro b/prototype/mech_pcbs/stator_base_pcb/stator_base_pcb.kicad_pro index 769f78b..08c7256 100644 --- a/prototype/mech_pcbs/stator_base_pcb/stator_base_pcb.kicad_pro +++ b/prototype/mech_pcbs/stator_base_pcb/stator_base_pcb.kicad_pro @@ -12,6 +12,14 @@ "courtyard_line_width": 0.049999999999999996, "dimension_precision": 1, "dimension_units": 0, + "dimensions": { + "arrow_length": 1270000, + "extension_offset": 500000, + "keep_text_aligned": true, + "suppress_zeroes": false, + "text_position": 0, + "units_format": 1 + }, "fab_line_width": 0.09999999999999999, "fab_text_italic": false, "fab_text_size_h": 1.0, @@ -49,38 +57,45 @@ ], "drc_exclusions": [], "meta": { - "version": 0 + "version": 1 }, "rule_severities": { + "annular_width": "error", "clearance": "error", "copper_edge_clearance": "error", "courtyards_overlap": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", "drill_too_small": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "hole_clearance": "error", "hole_near_hole": "error", "invalid_outline": "error", "item_on_disabled_layer": "error", "items_not_allowed": "error", "keepout": "error", + "length_out_of_range": "error", "malformed_courtyard": "error", "microvia_drill_too_small": "error", - "microvia_too_small": "error", "missing_courtyard": "ignore", "missing_footprint": "warning", + "net_conflict": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_over_copper": "error", + "silk_overlap": "error", + "skew_out_of_range": "error", + "too_many_vias": "error", "track_dangling": "warning", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", "unresolved_variable": "error", - "via_annulus": "error", "via_dangling": "warning", "via_hole_larger_than_pad": "error", - "via_too_small": "error", "zone_has_empty_net": "error", "zones_intersect": "error" }, @@ -95,6 +110,7 @@ "min_microvia_drill": 0.09999999999999999, "min_through_hole_diameter": 0.3, "min_track_width": 0.19999999999999998, + "min_via_annular_width": 0.049999999999999996, "min_via_annulus": 0.049999999999999996, "min_via_diameter": 0.39999999999999997, "solder_mask_clearance": 0.0, @@ -111,6 +127,7 @@ "drill": 0.4 } ], + "zones_allow_external_fillets": false, "zones_use_no_outline": false }, "layer_presets": [] @@ -119,6 +136,179 @@ "cvpcb": { "equivalence_files": [] }, + "erc": { + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 1, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2 + ] + ], + "rule_severities": { + "bus_definition_conflict": "error", + "bus_label_syntax": "error", + "bus_to_bus_conflict": "error", + "bus_to_net_conflict": "error", + "different_unit_footprint": "error", + "different_unit_net": "error", + "duplicate_sheet_names": "error", + "global_label_dangling": "warning", + "hier_label_mismatch": "error", + "label_dangling": "error", + "lib_symbol_issues": "warning", + "multiple_net_names": "warning", + "net_not_bus_member": "warning", + "no_connect_connected": "error", + "no_connect_dangling": "error", + "pin_not_connected": "error", + "pin_not_driven": "error", + "pin_to_pin": "warning", + "similar_labels": "warning", + "unresolved_variable": "error", + "wire_dangling": "error" + } + }, "libraries": { "pinned_footprint_libs": [], "pinned_symbol_libs": [] @@ -139,6 +329,8 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, @@ -157,14 +349,44 @@ "netlist": "", "specctra_dsn": "", "step": "", - "vmrl": "" + "vmrl": "", + "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { + "drawing": { + "default_bus_thickness": 12.0, + "default_junction_size": 40.0, + "default_line_thickness": 6.0, + "default_text_size": 50.0, + "default_wire_thickness": 6.0, + "field_names": [], + "intersheets_ref_prefix": "", + "intersheets_ref_short": false, + "intersheets_ref_show": false, + "intersheets_ref_suffix": "", + "pin_symbol_size": 25.0, + "text_offset_ratio": 0.3 + }, "legacy_lib_dir": "", - "legacy_lib_list": [] + "legacy_lib_list": [], + "meta": { + "version": 0 + }, + "net_format_name": "", + "page_layout_descr_file": "", + "plot_directory": "", + "spice_adjust_passive_values": false, + "spice_external_command": "spice \"%I\"", + "subpart_first_id": 65, + "subpart_id_separator": 0 }, - "sheets": [], + "sheets": [ + [ + "a9431c1e-4743-4297-a4a1-6e319184261a", + "" + ] + ], "text_variables": {} } |