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| author | jaseg <git@jaseg.de> | 2020-11-26 12:39:21 +0100 |
|---|---|---|
| committer | jaseg <git@jaseg.de> | 2020-11-26 12:39:21 +0100 |
| commit | 9b5625f12ae067a1583252d41febef848f055588 (patch) | |
| tree | 71ce1935254fec9bca064aa08dfe6eb7ef0e0c3e | |
| parent | 451904a0c5fae3bd28d35c7128df3a9db1a04b26 (diff) | |
| download | ihsm-9b5625f12ae067a1583252d41febef848f055588.tar.gz ihsm-9b5625f12ae067a1583252d41febef848f055588.tar.bz2 ihsm-9b5625f12ae067a1583252d41febef848f055588.zip | |
Make firmware build and run
| -rw-r--r-- | prototype/fw/include/global.h | 4 | ||||
| -rw-r--r-- | prototype/fw/openocd.cfg | 5 | ||||
| -rw-r--r-- | prototype/fw/src/main.c | 43 | ||||
| -rw-r--r-- | prototype/fw/tools/patch_system_init.py | 2 | ||||
| m--------- | prototype/fw/upstream/PyCortexMDebug | 0 |
5 files changed, 51 insertions, 3 deletions
diff --git a/prototype/fw/include/global.h b/prototype/fw/include/global.h index 138cbc9..d0c56d7 100644 --- a/prototype/fw/include/global.h +++ b/prototype/fw/include/global.h @@ -12,4 +12,8 @@ #include <generated/stm32_device.h> +#define APB1_PRESC (1<<(APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos])) +#define APB2_PRESC (1<<(APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2_Msk) >> RCC_CFGR_PPRE2_Pos])) +#define AHB_PRESC (1<<(AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE_Msk) >> RCC_CFGR_HPRE_Pos])) + #endif /* __GLOBAL_H__ */ diff --git a/prototype/fw/openocd.cfg b/prototype/fw/openocd.cfg index 5952538..51b3024 100644 --- a/prototype/fw/openocd.cfg +++ b/prototype/fw/openocd.cfg @@ -2,9 +2,10 @@ telnet_port 4444 gdb_port 3333 source [find interface/stlink-v2.cfg] -#adapter_khz 10000 - source [find target/stm32f3x_stlink.cfg] +# Overwrite init handler since stm32f3x.cfg just stomps all over our adapter_khz setting +stm32f3x.cpu configure -event reset-init { stm32f3x_default_reset_init; adapter_khz 1000 } + init arm semihosting enable diff --git a/prototype/fw/src/main.c b/prototype/fw/src/main.c index a6b265b..de920eb 100644 --- a/prototype/fw/src/main.c +++ b/prototype/fw/src/main.c @@ -2,7 +2,50 @@ #include <global.h> int main(void) { + + RCC->AHBENR |= RCC_AHBENR_GPIOAEN; + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + + GPIOA->MODER |= (2 << GPIO_MODER_MODER9_Pos); + GPIOA->AFR[1] = (7 << (9-8)*4); + + SystemCoreClockUpdate(); + int apb2_clock = SystemCoreClock / APB2_PRESC; + + int baudrate = 115200; + + USART1->CR1 = USART_CR1_MME | USART_CR1_TE; + USART1->BRR = (apb2_clock + baudrate/2) / baudrate; + USART1->CR1 |= USART_CR1_UE; + + char s[12] = { + '0', '0', '0', '0', '0', + ' ', 'T', 'E', 'S', 'T', + '\n', '\0'}; + int line = 0; + char *c = s; + USART1->TDR = *(c++); /* Kick off transmission */ while (23) { + if (USART1->ISR & USART_ISR_TXE) { + for (int i=0; i<100; i++) + asm volatile ("nop"); + USART1->TDR = *(c++); + if (!*c) { + c = s; + line++; + int tmp = line; + tmp %= 100000; + s[0] = '0' + tmp/10000; + tmp %= 10000; + s[1] = '0' + tmp/1000; + tmp %= 1000; + s[2] = '0' + tmp/100; + tmp %= 100; + s[3] = '0' + tmp/10; + tmp %= 10; + s[4] = '0' + tmp; + } + } } } diff --git a/prototype/fw/tools/patch_system_init.py b/prototype/fw/tools/patch_system_init.py index 1c83f5e..a3e84f8 100644 --- a/prototype/fw/tools/patch_system_init.py +++ b/prototype/fw/tools/patch_system_init.py @@ -16,4 +16,4 @@ if __name__ == '__main__': if line.strip().startswith('SCB->VTOR'): print(' SCB->VTOR = (uint32_t)&g_pfnVectors;') else: - print(line) + print(line.rstrip()) diff --git a/prototype/fw/upstream/PyCortexMDebug b/prototype/fw/upstream/PyCortexMDebug -Subproject 77e9717a0e7c5b44214bdf70fbddf376cf2e8a7 +Subproject 89c567b2847e1d3349b3bec64c3efa76f1ccf98 |